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Berkeley ELENG 141 - CMOS Inverter VTC Propagation Delay

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1EE141CMOS InverterVTCPropagation DelayEE141- Fall 2002Lecture 62EE141Today’s lectureContinuing analysis of a CMOS inverterVoltage transfer characteristicPropagation delayEE141MOS Transistor as a SwitchDischarging a capacitor• Can solve:()DSDDvii =dtdVCiDSD=3EE141MOS Transistor as a SwitchTraversed pathEE141MOS Transistor as a SwitchSolving the integral:Averaging resistances:4EE141Equivalent ResistanceW/L=1, L=0.25µmEE141Voltage TransferCharacteristic5EE141PMOS Load LinesVDSpIDpVGSp=-2.5VGSp=-1VDSpIDnVin=0Vin=1.5VoutIDnVin=0Vin=1.5Vin=VDD+VGSpIDn=-IDpVout=VDD+VDSpVoutIDnVin=VDD+VGSpIDn=-IDpVout=VDD+VDSpEE141CMOS Inverter Load CharacteristicsIDnVoutVin=2.5Vin=2Vin=1.5Vin=0Vin=0.5Vin=1NMOSVin=0Vin=0.5Vin=1Vin=1.5Vin=2Vin=2.5Vin=1Vin=1.5PMOS6EE141CMOS Inverter VTCVoutVin0.5 1 1.5 2 2.50.5 1 1.5 2 2.5NMOS resPMOSoffNMOS satPMOS satNMOS offPMOSresNMOS satPMOSresNMOSresPMOS satEE141Switching Threshold as afunction of Transistor Ratio1001010.80.911.11.21.31.41.51.61.71.8MV(V)Wp/Wn7EE141Determining VIHand VILVOHVOLVinVoutVMVILVIHA simplifiedapproachEE141Inverter Gain0 0.5 1 1.5 2 2.5-18-16-14-12-10-8-6-4-20Vin (V)gain8EE141Gain as a function of VDD0 0.05 0.1 0.15 0.200.050.10.150.2Vin (V)Vout (V)0 0.5 1 1.5 2 2.500.511.522.5Vin (V)Vout(V)Gain=-1EE141Simulated VTC0 0.5 1 1.5 2 2.500.511.522.5Vin (V)Vout(V)9EE141Impact of Process Variations0 0.5 1 1.5 2 2.500.511.522.5Vin(V)Vout(V)Good PMOSBad NMOSGoodNMOSBad PMOSNominalEE141MOS CapacitancesDynamic Behavior10EE141Dynamic Behavior of MOS TransistorDSGBCGDCGSCSBCDBCGBEE141The Gate Capacitance11EE141Gate CapacitanceSDGCGCSDGCGCSDGCGCCut-offResistive SaturationMost important regions in digital design: saturation and cut-offEE141Gate CapacitanceWLCoxWLCox22WLCox3CGCCGCSVDS/(VGS-VT)CGCD01CGCCGCS=CGCDCGC BWLCoxWLCox2VGSCapacitance as a function of VGS(with VDS = 0)Capacitance as a function of thedegree of saturation12EE141Diffusion CapacitanceEE141Junction Capacitance13EE141Linearizing the Junction CapacitanceReplace non-linear capacitance bylarge-signal equivalent linear capacitancewhich displaces equal chargeover voltage swing of interestEE141Capacitances in 0.25µmCMOS process14EE141.MODEL Parameters MOS1.MODEL Modname NMOS/PMOS <VTO=VTO...>EE141Computing the CapacitancesVDDVDDVinVoutM1M2M3M4Cdb2Cdb1Cgd12CwCg4Cg3Vout2FanoutInterconnectVoutVinCLSimplifiedModel15EE141The Miller EffectVinM1Cgd1Vout∆V∆VVinM1Vout∆V∆V2Cgd1“A capacitor experiencing identical but opposite voltage swingsat both its terminals can be replaced by a capacitor to ground,whose value is two times the original value.”EE141Computing the Capacitances16EE141CMOS InvertersPolysiliconInOutMetal1VDDGNDPMOSNMOS1.2µm=2λλλλEE141Propagation Delay17EE141CMOS Inverter Propagation DelayApproach 1VDDVoutVin=VDDCLIavtpHL=CLVswing/2IavCLknVDD~EE141CMOS Inverter Propagation DelayApproach 2VDDVoutVin=VDDRonCLtpHL= f(Ron.CL)=0.69RonCLtVoutVDDRonCL10.5ln(0.5)0.3618EE1410 0.5 1 1.5 2 2.5x 10-10-0.500.511.522.53t (sec)Vout(V)Transient Responsetp=0.69CL(Reqn+Reqp)/2?tpLHtpHLEE141Design for PerformanceKeep capacitances smallIncrease transistor sizes» watch out for self-loading!Increase VDD(?)19EE141Delay as a function of VDD0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.411.522.533.544.555.5VDD(V)tp(normalized)EE1412 4 6 8 10 12 1422.22.42.62.833.23.43.63.8x 10-11Stp(sec)Device Sizing(for fixed load)Self-loading effect:Intrinsic capacitancesdominate20EE1411 1.5 2 2.5 3 3.5 4 4.5 533.544.55x 10-11βtp(sec)NMOS/PMOS ratiotpLHtpHLtpβ =Wp/WnEE141Impact of Rise Time on DelaytpHL(nsec)0.350.30.250.20.15trise(nsec)10.80.60.40.20tp= tstep(i)+ηtstep(i-1)21EE141The Sub-Micron MOS TransistorThreshold VariationsSubthreshold ConductionParasitic ResistancesEE141Threshold VariationsVTLLong-channel thresholdLow VDSthresholdThreshold as a function ofthe length (for lowVDS)Drain-induced barrier lowering(for low L)VDSVT22EE141Sub-Threshold Conduction0 0.5 1 1.5 2 2.510-1210-1010-810-610-410-2VGS(V)ID(A)VTLinearExponentialQuadraticTypical values for S:60 .. 100 mV/decadeThe Slope FactoroxDnkTqVDCCneIIGS+=1,~0S is ∆VGSfor ID2/ID1=10EE141Sub-Threshold IDvs VGSVDSfrom 0to 0.5V−=−kTqVnkTqVDDSGSeeII 1023EE141Sub-Threshold IDvs VDS()DSkTqVnkTqVDVeeIIDSGS⋅+−=−λ110VGSfrom 0 to


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Berkeley ELENG 141 - CMOS Inverter VTC Propagation Delay

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