EE1411EE1411IC ManufacturingEE141- Spring 2003Lecture 3EE1412Last LectureDesign Metrics (part 1)TodayDesign metrics (wrap-up)IC manufacturingEE1412EE1413AdministriviaDiscussion sessions start this week. Only one thisweek (Dejan is still stuck)We 2-3pm in 203 McLaughlinHomework 1 due on Th» If you have problems running SPICE, check with HuifangLabs start next week!» Make sure to get your card key coded for 353 Cory» Temporary logins have been provided for the PCs in 353Cory.– Login: ee141-temp– Passward: tempaccountEE1414The EE141 Week at a GlanceMTuWThF89101112123456Lab(both)353 CoryLab(Dejan)353 CoryDISC*(Dejan)203McLaughlinLec(Jan)203 McLaughlin<- ProblemSets DueOH(Jan) 511CoryLec(Jan)203 McLaughlin* Discussion sections will cover identical materialTA mtngBWRCLab(Huifang)353 CoryOH(Dejan)289CoryOH(Huifang)289CoryDISC*(Huifang)TBDEE1413EE1415Design Metrics (wrap-up)How to quantify thequality of a gate?So far : cost & reliabilityToday: speed & powerEE1416Delay DefinitionsVouttftpHLtpLHtrtVint90%10%50%50%EE1414EE1417Ring Oscillatorv0v1v5v1v2v0v3v4v5T=2×tp×NEE1418AFirst-OrderRCNetworkvoutvin CRtp=ln(2)τ =0.69RCImportant model – matches delay of inverterEE1415EE1419Power DissipationInstantaneous power:p(t)=v(t)i(t)=Vsupplyi(t)Peak power:Ppeak= VsupplyipeakAverage power:()∫∫++==TttTttsupplysupplyavedttiTVdttpTP )(1EE14110Energy and Energy-DelayPower-Delay Product (PDP) =E = Energy per operation = Pav×tpEnergy-Delay Product (EDP) =quality metric of gate = E×tpEE1416EE14111AFirst-OrderRCNetworkE01→Pt()dt0T∫Vddisupplyt()dt0T∫VddCLdVout0Vdd∫CLVdd•2== = =EcapPcapt()dt0T∫Vouticapt()dt0T∫CLVoutdVout0Vdd∫12---CLVdd•2== = =voutvin CLREE14112CMOSManufacturingProcessEE1417EE14113CMOS ProcessEE14114AModernCMOSProcessp-welln-wellp+p-epiSiO2AlCupolyn+SiO2p+gate-oxideTungstenTiSi2DualDual--Well TrenchWell Trench--Isolated CMOS ProcessIsolated CMOS ProcessEE1418EE14115Circuit Under DesignThis two-inverter circuit (of Figure 3.25 in the text) will bemanufactured in a twin-well process.VDDVDDVinVoutM1M2M3M4Vout2EE14116Circuit LayoutEE1419EE14117The Manufacturing ProcessFor a great tour through the process and its different steps, checkhttp://www.fullman.com/semiconductors/semiconductors.htmlhttp://bwrc.eecs.berkeley.edu/Classes/IcBookFor a complete walk-through of the process (64 steps), check theBook web-pageEE14118oxidationopticalmaskprocessstepphotoresist coatingphotoresistremoval (ashing)spin, rinse, dryacid etchphotoresiststepper exposuredevelopmentTypical operations in a singlephotolithographic cycle (from [Fullman]).Photo-Lithographic ProcessEE14110EE14119Patterning of SiO2Si-substrateSi-substrateSi-substrate(a) Silicon base material(b) After oxidation and depositionof negative photoresist(c) Stepper exposurePhotoresistSiO2UV-lightPatternedoptical maskExposed resistSiO2Si-substrateSi-substrateSi-substrateSiO2SiO2(d) After development and etching of resist,chemical or plasma etch of SiO2(e) After etching(f) Final result after removal of resistHardened resistHardened resistChemical or plasmaetchEE14120CMOS Process at a GlanceDefine active areasEtch and fill trenchesImplant well regionsDeposit and patternpolysilicon layerImplant source and drainregions and substrate contactsCreate contact and via windowsDeposit and pattern metal layersEE14111EE14121CMOS Process Walk-Throughp+p-epi(a) Base material: p+ substratewith p-epi layerp+(c) After plasma etch of insulatingtrenches using the inverse ofthe active area maskp+p-epiSiO23SiN4(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)EE14122CMOS Process Walk-ThroughSiO2(d) After trench filling, CMPplanarization, and removal ofsacrificial nitride(e) After n-well andVTpadjust implantsn(f) After p-well andVTnadjust implantspEE14112EE14123CMOS Process Walk-Through(g) After polysilicon depositionand etchpoly(silicon)(h) After n+ source/drain andp+source/drain implants. Thesep+n+steps also dope the polysilicon.(i) After deposition of SiO2insulator and contact hole etch.SiO2EE14124CMOS Process Walk-Through(j) After deposition andpatterning of first Al layer.Al(k) After deposition of SiO2insulator, etching of via’s,deposition and patterning ofsecond layer of Al.AlSiO2EE14113EE14125Advanced MetalizationEE14126Advanced MetalizationEE14114EE14127Jan M. RabaeyDesign RulesEE141283D PerspectivePolysiliconAluminumEE14115EE14129Design RulesInterface between designer and processengineerGuidelines for constructing process masksUnit dimension: Minimum line width» scalable design rules: lambda parameter» absolute dimensions (micron rules)EE14130CMOS Process LayersLayerPolysiliconMetal1Metal2Contact To PolyContact To DiffusionViaWell (p,n)Active Area (n+,p+)Color RepresentationYellowGreenRedBlueMagentaBlackBlackBlackSelect (p+,n+)GreenEE14116EE14131Layers in 0.25 µmCMOSprocessEE14132Intra-Layer Design RulesMetal2431090WellActive33Polysilicon22Different PotentialSame PotentialMetal1332Contactor ViaSelect2or62HoleEE14117EE14133Transistor Layout1253TransistorEE14134Vias and Contacts121Vi aMetal toPoly ContactMetal toActive Contact1254322EE14118EE14135Select Layer133222WellSubstrateSelect35EE14136CMOS Inverter LayoutAA’np-substrateFieldOxidep+n+InOutGNDVDD(a) Layout(b) Cross-Section along A-A’AA’EE14119EE14137Layout EditorEE14138Design Rule Checkerpoly_not_fet to all_diff minimum spacing = 0.14 um.EE14120EE14139Sticks Diagram13InOutVDDGNDStick diagram of inverter• Dimensionless layout entities• Only topology is important• Final layout generated by“compaction” programEE14140Next LectureThe inverter at a glanceThe MOS
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