EE141 EE141 Spring 2004 Digital Integrated Circuits Lecture 30 PERSPECTIVES 1 EE141 EE141 S04 Administrative Stuff Homework 10 posted just for practice No need to turn in hw 9 due today Normal office hours next week HKN review today Your feedback is important Final covers all material covered in class Precise overview to be posted on web site Review session the day before the final TBA 2 EE141 EE141 S04 1 EE141 Project 2 some exciting results Most projects focused on non restoring combined with mostly pass transistor based implementation Some great alternatives Look up tables Carry select combined with concurrency Exploit the specs Grades Mean 16 88 Median 16 75 Stddev 2 01 Max 20 3 EE141 EE141 S04 Memory 4 EE141 EE141 S04 2 EE141 Semiconductor Memory Classification Read Write Memory Random Access Non Random Access Non Volatile Read Write Memory Read Only Memory EPROM Mask Programmed 2 E PROM SRAM FIFO DRAM LIFO Programmable PROM FLASH Shift Register CAM 5 EE141 EE141 S04 6 transistor CMOS SRAM Cell WL V DD M2 M5 Q M1 BL M4 Q M6 M3 BL 6 EE141 EE141 S04 3 EE141 Resistance load SRAM Cell WL V DD RL M3 BL RL Q Q M1 M4 BL M2 Static power dissipation Want R L large Bit lines precharged to V DD to address t p problem 7 EE141 EE141 S04 3 Transistor DRAM Cell BL 2 BL 1 WWL WWL RWL M3 X M1 CS M2 RWL V DD 2 V T X BL 1 V DD BL 2 V DD 2 V T DV No constraints on device ratios Reads are non destructive Value stored at node X when writing a 1 VWWL VTn 8 EE141 EE141 S04 4 EE141 3T DRAM Layout BL2 BL1 GND RWL M3 M2 WWL M1 9 EE141 EE141 S04 1 Transistor DRAM Cell Write CS is charged or discharged by asserting WL and BL Read Charge redistribution takes places between bit line and storage capacitance CS V VBL V PRE V BIT V PRE C S CBL Voltage swing is small typically around 250 mV 10 EE141 EE141 S04 5 EE141 DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line due to charge redistribution read out DRAM memory cells are single ended in contrast to SRAM cells The read out of the 1T DRAM cell is destructive read and refresh operations are necessary for correct operation Unlike 3T cell 1T cell requires presence of an extra capacitance that must be explicitly included in the design When writing a 1 into a DRAM cell a threshold voltage is lost This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD 11 EE141 EE141 S04 Sense Amp Operation V BL V 1 V PRE DV 1 V 0 Sense amp activated Word line activated t 12 EE141 EE141 S04 6 EE141 1 T DRAM Cell Capacitor M 1 word line Metal word line SiO2 Poly n Field Oxide n Poly Inversion layer induced by plate bias Diffused bit line Cross section Polysilicon gate Polysilicon plate Layout Uses Polysilicon Diffusion Capacitance Expensive in Area 13 EE141 EE141 S04 SEM of poly diffusion capacitor 1T DRAM 14 EE141 EE141 S04 7 EE141 Advanced 1T DRAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Refilling Poly Transfer gate Isolation Storage electrode Storage Node Poly Si Substrate 2nd Field Oxide Trench Cell Stacked capacitor Cell 15 EE141 EE141 S04 EE 141 Summary Digital CMOS design is kicking and well Some major challenges down the road Cost Power consumption Robustness Complexity Some new circuit solutions and design methodologies are bound to emerge 16 EE141 EE141 S04 8 EE141 18nm FinFET Double gate structure raised source drain 400 Gate 1 50 V Gate Silicon Fin Source BOX Drain Si fin Body Id uA um 350 1 25 V 300 250 200 1 00 V 0 75 V 150 100 50 0 50 V 0 25 V 0 X Huang et al 1999 IEDM p 67 70 1 5 1 0 0 5 Vd V 0 0 17 EE141 EE141 S04 And after that the nano age NEMS Nanotube Organic polymer NanoNano optics Nanowire Molecular Quantum Dots 18 EE141 EE141 S04 9 EE141 With ever more Exotic Behaviors Scaled MOS 2000 Nanometer MOS 2005 Beyond MOS 2010 Courtesy R Rutenbar CMU 19 EE141 EE141 S04 Cost Mask cost in 90nm technology is over 1M In 130nm is slowly dropping from 700k Bugs are very expensive Design effort increases in DSM Cost of new tools Non recurring costs dominate the price effectiveness of low volume ASICs Need to have a product that can fit multiple applications customers flexibility 20 EE141 EE141 S04 10 EE141 Power will be a problem 100000 18KW 5KW 1 5KW 500W Power Watts 10000 1000 Pentium proc 100 286 486 8086 386 8085 8080 8008 1 4004 10 S Borkar 0 1 1971 1974 1978 1985 1992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive 21 EE141 EE141 S04 Logic Transistors Chip 100 000 000 10 1 000 000 Transistor Staff Month 10 000 000 100 000 35 58 Yr compound Complexity growth rate 1 000 000 10 000 100 000 1 000 10 000 x x x x 1 000 x 100 10 2009 2003 2005 2007 2001 1999 1997 1995 21 Yr compound Productivity growth rate 1991 1987 1 1983 10 1985 2 5 x 1989 x 1993 100 Productivity Trans Staff Month 10 000 000 1981 Logic Transistors per Chip K The Productivity Gap Source SEMATECH 22 EE141 EE141 S04 11 EE141 From ASIC Design Standard Cells Cell structure hidden under interconnect layers 23 EE141 EE141 S04 To Flexible Solutions RAM based FPGA Xilinx XC4025 24 EE141 EE141 S04 12 EE141 Xilinx Vertex II 18 embedded multipliers PowerPC 3 1 Gbs Serial Interface 25 EE141 EE141 S04 Flexibility and Efficiency Prog Mem Flexibility P MAC Addr Unit Gen Embedded Processor DSP e g TI 320CXX Reconfigurable Processor Embedded FPGA Direct Mapped Hardware EE141 EE141 S04 Inefficiency Power Area 26 13 EE141 The Challenge of the Next Decade The Deep Sub Micron DSM Effect 0 25 DSM 1 DSM Macroscopic Issues Microscopic Problems Time to Market Millions of Gates High Level Abstractions Reuse IP Portability Predictability etc Wiring Load Management Noise Crosstalk Reliability Manufacturability Complexity LRC ERC Accurate Power Prediction Accurate Delay Prediction etc Everything Looks a Little Different and There s a Lot of Them 27 EE141 EE141 S04 That s all Folks Thanks for the fun semester And good luck in your future endeavors 28 EE141 EE141 S04 14
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