EE1411EE1411EE141-S04EE141EE141--Spring 2004Spring 2004Digital Integrated Digital Integrated CircuitsCircuitsLecture 27Lecture 27Power distributionPower distributionResistive interconnectResistive interconnectEE1412EE141-S04Administrative StuffAdministrative Stuff Make-up lecture on Monday 4-5:30pm Special office hours of Prof. Rabaey today 5-6:30pm at BWRC Homework 9 posted – due next Th 5pm Poster presentations next Tu. Sign up for time slot (office door of Prof. Rabaey). Poster template on web-site.EE1412EE1413EE141-S04Class MaterialClass Material Today’s lecture Power distribution RC Interconnect optimizationEE1414EE141-S04Power Power DistributionDistributionEE1413EE1415EE141-S04Impact of ResistanceImpact of Resistance We have already learned how to drive RC interconnect Impact of resistance is commonly seen in power supply distribution: IR drop Voltage variations Power supply is distributed to minimize the IR drop and the change in current due to switching of gatesEE1416EE141-S04RI Introduced NoiseRI Introduced NoiseM1XIR9RDVfpreDVVDDVDD2DV9IEE1414EE1417EE141-S04Resistance and the Power Resistance and the Power Distribution ProblemDistribution ProblemSource: Cadence••Requires fast and accurate peak current predictionRequires fast and accurate peak current prediction••Heavily influenced by packaging technologyHeavily influenced by packaging technologyBeforeBeforeAfterAfterEE1418EE141-S04Power DistributionPower Distribution Low-level distribution is in Metal 1 Power has to be ‘strapped’ in higher layers of metal. The spacing is set by IR drop, electromigration, inductive effects Always use multiple contacts on strapsEE1415EE1419EE141-S04Power and Ground DistributionPower and Ground DistributionGNDVDDLogicGNDVDDLogicGNDVDD(a) Finger-shaped network (b) Network with multiple supply pinsEE14110EE141-S043 Metal Layer Approach (EV4)3 Metal Layer Approach (EV4)3rd “coarse and thick” metal layer added to thetechnology for EV4 designPower supplied from two sides of the die via 3rd metal layer2nd metal layer used to form power grid90% of 3rd metal layer used for power/clock routingMetal 3Metal 2Metal 1Courtesy CompaqEE1416EE14111EE141-S044 Metal Layers Approach (EV5)4 Metal Layers Approach (EV5)4th “coarse and thick” metal layer added to thetechnology for EV5 designPower supplied from four sides of the dieGrid strapping done all in coarse metal90% of 3rd and 4th metals used for power/clock routingMetal 3Metal 2Metal 1Metal 4Courtesy CompaqEE14112EE141-S042 reference plane metal layers added to thetechnology for EV6 designSolid planes dedicated to Vdd/VssSignificantly lowers resistance of gridLowers on-chip inductance6 Metal Layer Approach 6 Metal Layer Approach ––EV6EV6Metal 4Metal 2Metal 1RP2/VddRP1/VssMetal 3Courtesy CompaqEE1417EE14113EE141-S04ElectromigrationElectromigration(1)(1)Limits dc-current to 1 mA/µmEE14114EE141-S04ElectromigrationElectromigration(2)(2)EE1418EE14115EE141-S04The Impact of The Impact of ResistivityResistivityCN-1CNC2R1R2C1TrVinRN-1 RN0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 500.511.522.5time (nsec)voltage (V)x= L/10 x = L/4 x = L/2 x= L 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 500.511.522.5time (nsec)voltage (V)x= L/10 x = L/4 x = L/2 x= L Diffused signal Diffused signal propagationpropagationDelay ~ LDelay ~ L22The distributed The distributed rcrc--linelineEE14116EE141-S04The Global Wire ProblemThe Global Wire ProblemChallenges No further improvements to be expected after the introduction of Copper (superconducting, optical?) Design solutions Use of fat wires Insert repeaters — but might become prohibitive (power, area) Efficient chip floorplanning Towards “communication-based” design How to deal with latency? Is synchronicity an absolute necessity?()outwwdoutdwwdCRCRCR693.0CR377.0T+++=EE1419EE14117EE141-S04Interconnect:Interconnect:# of Wiring Layers# of Wiring Layers# of metal layers is steadily increasing due to:• Increasing die size and device count: we need more wires and longer wires to connect everything• Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC substratepolyM1M2M3M4M5M6TinsHWSρ = 2.2 µΩ-cm0.25 µm wiring stackMinimum Widths (Relative)0.00.51.01.52.02.53.03.51.0µ 0.8µ 0.6µ 0.35µ 0.25µM5M4M3M2M1PolyMinimum Spacing (Relative)0.00.51.01.52.02.53.03.54.01.0µ 0.8µ 0.6µ 0.35µ 0.25µM5M4M3M2M1PolyEE14118EE141-S04Interconnect Projections: CopperInterconnect Projections: Copper Copper is planned in full sub-0.25 µm process flows and large-scale designs (IBM, Motorola, IEDM97) With cladding and other effects, Cu ~ 2.2 µΩ-cm vs. 3.5 for Al(Cu) ⇒40% reduction in resistance Electromigration improvement; 100X longer lifetime (IBM, IEDM97) Electromigration is a limiting factor beyond 0.18 µm if Al is used (HP, IEDM95)ViasEE14110EE14119EE141-S04Diagonal WiringDiagonal WiringyxdestinationManhattansourcediagonal• 20+% Interconnect length reduction• Clock speedSignal integrityPower integrity• 15+% Smaller chips plus 30+% via reductionCourtesy Cadence X-initiativeEE14120EE141-S04Reducing RCReducing RC--delaydelayRepeaterEE14111EE14121EE141-S04Repeater Insertion (Revisited)Repeater Insertion (Revisited)Taking the repeater loading into accountFor a given technology and a given interconnect layer, there exiFor a given technology and a given interconnect layer, there exists sts an optimal length of the wire segments between repeaters. The an optimal length of the wire segments between repeaters. The delay of these wire segments is delay of these wire segments is independent of the routing layer!independent of the routing layer!EE14122EE141-S04INTERCONNECTINTERCONNECTDealing with InductanceDealing with InductanceEE14112EE14123EE141-S04L L di/dtdi/dtImpact of inductance on supply voltages:• Change in current induces the change in voltage• Longer supply lines have larger LCLV’DDVDDLi(t)VoutVinGND ’LEE14124EE141-S04L L di/dtdi/dt: Simulation: SimulationtttvoutiLvL20mA40mA5V0.2V0.01.02.03.04.05.0Vout(V)01020IL (mA)246810t (nsec)-0.3-0.10.10.30.5VL(V)tfall = 0.5 nsectfall = 4 nsecSignals Waveforms for Output Driver connected To Bonding Pads(a) vout; (b) iL and (c) vL.The Results of an Actual Simulation are Shown on the Right Side.EE14113EE14125EE141-S04Choosing the Right PinChoosing the Right PinChipLL´Bonding wireMountingcavityLeadframePinEE14126EE141-S04Decoupling
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