EE1411EECS1411Lecture #18EE141EE141--Fall 2008Fall 2008Digital Integrated Digital Integrated CircuitsCircuitsLecture 18Lecture 18RatioedRatioedand Pass and Pass Transistor LogicTransistor LogicEE1412EECS1412Lecture #18AnnouncementsAnnouncements Project #1 due Thursday Project #1 out today, due next Thurs. No lecture this Thurs. Midterm 2: Thurs. Nov. 6th, 6:30-8:00pm, 277 CoryEE1413EECS1413Lecture #18RatioedRatioedLogicLogicEE1414EECS1414Lecture #18RatioedRatioedLogicLogicVDDVSSPDNIn1In2In3FRLLoadVDDVSSIn1In2In3FVDDVSSPDNIn1In2In3FVSSPDNResistiveDepletionLoadPMOSLoad(a) resistive load (b) depletion load NMOS (c) pseudo-NMOSVT < 0Goal: build gates faster/smaller than staticcomplementary CMOSEE1415EECS1415Lecture #18Ratioed LogicRatioed Logic Spend power for speed Use pseudo nMOS NOR gates, not NAND gates DC characteristics: VOH= VDD VOLdepends on PMOS to NMOS ratioWWW WEE1416EECS1416Lecture #18PseudoPseudo--NMOS VTCNMOS VTC0.0 0.5 1.0 1.5 2.0 2.50.00.51.01.52.02.53.0Vin[V]Vout[V]W/Lp = 4W/Lp = 2W/Lp = 1W/Lp = 0.25W/Lp = 0.5EE1417EECS1417Lecture #18Ratioed Logic LERatioed Logic LE Rising and falling delays aren’t the same Calculate LE for the two edges separately For tpLH: Cgate= WCGCinv= (3/2)WCGLELH= EE1418EECS1418Lecture #18Ratioed Logic LE (pullRatioed Logic LE (pull--down edge)down edge)WWW W What is LE for tpHL? Switch model would predict Reff= Rn||Rp Would that give the right answer for LE?EE1419EECS1419Lecture #18Response on Falling EdgeResponse on Falling Edge Time constant is smaller, but it takes more time to complete 50% VDDtransient. Rp actually takes some current away from discharging CRpRnCvo(t)0123400.51vo(t)/VDDtRp=RnRp=2RnRp=4RnRp=∞CRpRnRpRn⋅+⋅=ττ/1)(tDDoeRpRnRnRpRnRnVtv−⎟⎟⎠⎞⎜⎜⎝⎛+−++=EE14110EECS14110Lecture #18RatioedRatioedLogic PullLogic Pull--down Delaydown Delay Think in terms of the current driving Cload When you have a conflict between currents Available current is the difference between the two In pseudo-nMOS case: (Works because Rp >> Rn for good noise margin)()1drive drive1RnR= R=11-Rn-Rn RpRpEE14111EECS14111Lecture #18Ratioed Logic LE (pullRatioed Logic LE (pull--down edge)down edge) For tpHL(assuming Rsqp= 2Rsqn): Rgate= Rn/(1-Rn/Rp) = 2Rn Rinv= Rn Cgate= WCGCinv= 3WCG LEHL= LE is lower than an inverter! But have static power dissipation…WWW W2WWEE14112EECS14112Lecture #18Improved Loads (2)Improved Loads (2)VDDVSSFOutVDDVSSF_bOutAABBM1 M2Differential Cascode Voltage Switch Logic (DCVSL)EE14113EECS14113Lecture #18DCVSL Transient ResponseDCVSL Transient Response0 0.2 0.4 0.6 0.8 1.0-0.50.51.52.5Time [ns]Vol ta ge[V]A BA BA,BA,BEE14114EECS14114Lecture #18DCVSL Example1DCVSL Example1EE14115EECS14115Lecture #18PassPass--TransistorTransistorLogicLogicEE14116EECS14116Lecture #18PassPass--Transistor LogicTransistor LogicInputsSwitchNetworkOutOutABBB• N transistors• No static consumptionEE14117EECS14117Lecture #18Example: AND GateExample: AND GateBBAF = AB0EE14118EECS14118Lecture #18NMOSNMOS--Only LogicOnly LogicVDDInOutx0.5µm/0.25µm0.5µm/ 0.2 5µm1.5µm/ 0.2 5µm0 0.5 1 1.5 20.01.02.03.0Time [ns]Voltage[V]xOutInEE14119EECS14119Lecture #18NMOSNMOS--only Switchonly SwitchA = 2.5 VBC = 2.5VCLA = 2.5 VC = 2.5 VBM2M1MnThreshold voltage loss causesstatic power consumptionVBdoes not pull up to 2.5V, but 2.5V -VTNNMOS has higher threshold than PMOS (body effect)EE14120EECS14120Lecture #18NMOS Only Logic: NMOS Only Logic: Level Restoring TransistorLevel Restoring TransistorM2M1MnMrOutABVDDVDDLevel RestorerX• Advantage: Full Swing• Restorer adds capacitance, takes away pull down current at X• Ratio problemEE14121EECS14121Lecture #18Restorer SizingRestorer Sizing0 100 200 300 400 5000.01.02.0W/Lr=1.0/0.25 W/Lr=1.25/0.25 W/Lr=1.50/0.25 W/Lr=1.75/0.25 Voltage [V]Time [ps]3.0•Upper limit on restorer size•Pass-transistor pull-downcan have several transistors in stackEE14122EECS14122Lecture #18Pass Transistor Logic LEPass Transistor Logic LE What is LE of “gate” shown below for A and B inputs? Hint: Can you answer this question with only the information shown below?EE14123EECS14123Lecture #18Pass Transistor Logic LEPass Transistor Logic LE In CMOS, a “gate” is defined only when trace a connection all the way back to a supply Otherwise don’t know what drive resistance really isEE14124EECS14124Lecture #18Pass Transistor Logic LEPass Transistor Logic LEEE14125EECS14125Lecture #18Complementary Pass Transistor LogicComplementary Pass Transistor LogicABABBBB BABABF=ABF=ABF=A+BF=A+BB BAAAAF=A⊕ΒÝF=A⊕ΒÝOR/NOREXOR/NEXORAND/NANDFFPass-TransistorNetworkPass-TransistorNetworkAABBAABBInverse(a)(b)EE14126EECS14126Lecture #18CPL Level RestoreCPL Level RestoreEE14127EECS14127Lecture #18Solution 2: Transmission GateSolution 2: Transmission GateABCCABCCBCLC = 0 VA = 2.5 VC = 2.5 VEE14128EECS14128Lecture #18Resistance of Transmission GateResistance of Transmission GateVout0 V2.5 V2.5 VRnRp0. 0 1. 0 2. 00 10 20 30 Vout, VResistance, ohmsRnRpRn || RpEE14129EECS14129Lecture #18PassPass--Transistor Based MultiplexerTransistor Based MultiplexerAM2M1BSSSFVDDGNDVDDIn1In2SSSSEE14130EECS14130Lecture #18Transmission Gate XORTransmission Gate XOREE14131EECS14131Lecture #18Next LectureNext Lecture Dynamic
View Full Document
Unlocking...