IEEE JOURNAL OF :;OLID-STATE CIRCUITS, VOL. 26>NO. 9, SEPTEMBER 19911265Variable-Taper CMOS BufferSrinivasa R. Vemuru and Arthur R. ThorbjornsenAbstract —A variable-taper (VT) approach to buffer design isproposed where the taper from one inverter stage to the next is afunction of the position of the inverter within the buffer chain.Though the minimum delay obtained by using a VT buffer isabout15~o more than the minimum delay obtained from conven-tional fixed-taper (ET) buffers, a small modification to theinitial stages of the VT buffer reduces this difference to less than2%. For similar delays, a VT buffer usually takes less area andconsumes less power than an IT buffer.I. INTRODUCTIONwITH the scaling down of device dimensions, thedifference in capacitance of the logic circuitry andthe output stages is ever increasing. Lin and Linholm [1]used a tapered chain of inverters where each inverter inthe buffer chain ch-ives another inverter which is ~f timesits own size. Several authors improved this model toinclude the no-lc~ad delays of the logic gate [2], short-circuit currents ir the signal transients [3], and the effectof the output capacitance of the driving stage [4]–[9]. Wepropose a tapered buffer model of which the taper factorfrom one inverte:: stage to the next is a variable depen-dent on the local ion of the inverter in the buffer chain.Two important factors considered in the design of thebuffers are the delay penalty factor l) and the areapenalty factor zl. The delay penalty factor is the ratio ofthe propagation clelay of the buffer chain to the propaga-tion delay of a logic-level inverter. The area penalty factoris the ratio of the buffer area to the area of a logic-levelinverter. InSecl.ion H, A and D are derived for avariable-taper (VT) buffer. In Section 111,the results areextended to include the self-load capacitance of the driv-ing inverter in the VT buffer design. Comparisons ofpower dissipations of fixed-taper (FT) and VT buffers aremade in Section IV. A modification to VT buffer designthat reduces the delay penalty factor of the buffer ispresented in Secl ion V.II. VARIABLE-TAPER(VT) BUFFERThe taper configuration of the n-stage VT buffer isshown in Fig. 1. The buffer is connected between logiccircuitry and out?ut capacitance. The capacitance of thelogic-level inverter is given as Ci, the logic-level conduc-tance is gi, and the logic-level inverter has a first-orderRC delay estimal e of ~ (r= Ci /gi) [6]. The sizes of theManuscript received February 22, 1991; revised May 17, 1991.The authors are with the Department of Electrical Engineering,University of Toledo, Toledo, OH 43606.IEEE Log Numbel 9101728.Fig. 1. VT model of a buffer.transistors in stages k + 1 and k are related by(:)k+l=~’+’(a(1)where ~U is a taper factor. Therefore, the sizes of theinverters in later stages of the buffer taper out at agreater rate compared to the initial stages. The conduc-tance, load, and delay of thek th stage areCk = pf+ D(k+W2c.1(3)The overall delay of the buffer,Too, is given as(5)To drive a capacitive load of CL, the number of stages inthe buffer, n, is given byThe delay penalty factor for the VT buffer, D., is given as(7)The area penalty factor for the variable taper buffer, A”,is given by(8)k=OThe expression for optimum ~U value for minimum delayin the buffer is given in [10] and Table I gives the optimal8U for the VT buffer for different ratios of CL/ Ci. It canbe seen that /30~Ptreduces for increasing values of theCL/ Ci. This is in contrast to the FT model where theoptimal delay is obtained when /3f = e for all CL/ Ciratios [11].The area penalty factor and delay penalty factor areplotted for different ratios of CL/ Ci for FT and VT0018-9200/91/0900-1265$01.00 01991 IEEE1266IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26,NO. 9, SEPTEMBER 1991TABLE IBETA VALUE FOR A MINIMUM DELAY OF A VT BUFFER ANDCOMPARISONOFTHEMINIMUMDELAYSOF !3 AND VTBUFFERDESIGNSFOR DIFFERENTCAPACITIVELOADS~6.66 10.04 13.75 17.14 20.85 24.24 27.969.25 12.52 15,50 18.78 21.76 25.04lo~10Area penal t y factor100(a)80L~v 60~.z2& ~.z~201001000 10000Area penal t y facto r(b)❑ Better VT Oesign❑ Better FT Oesign- VT+ FTFig. 2. Comparison of the delay penalty factor versus the area penaltyfactor of an FT buffer and a VT buffer design for different capacitiveloads: (a) CL /Ci = 102 and (b) CL /Ci = 104.buffer implementations in Fig. 2(a) and (b). Each point onthese cin-ves corresponds to a beta value. The beta valuescorresponding to the left of the minimum delay factorgive good designs; i.e., as the area penalty increases, thedelay penalty decreases. For the beta values correspond-ing to the points on the curve to the right of the minimumdelay penalty factor, the area penalty factor increaseswith increasing delay penalty factor. The shaded regioncorresponds to the region where the VT model gives abetter design, i.e., for the same delay, the area taken bythe VT buffer is less than that of the FT buffer, whereasthe FT model gives better designs in the cross-hatchedareas. In medium fan-out circuits (CL < 50Ci) that re-quire a one- or two-staged buffer, an FT model results inbetter designs. But, for driving high capacitive loads likeoff-chip circuitry, control drivers, and clock drivers, a VTbuffer results in more compact layouts for comparabledelay penalties. The minimum delay in a buffer chain isobtained when the taper from one inverter stage to thenext is constant [12], i.e., the FT designs give the mini-mum possible delays. Table I gives the minimum delaysobtained by using FT and VT implementations. Thesmallest delays obtained using the VT model are less than15% greater than the smallest delays obtained from anFT model.III. EFFECTOFTHEOUTPUTCAPACITANCEONTHEBUFFERDESIGNThe effect of the inherent output capacitance in thedesign of an FT buffer was discussed by Li et al. [6]. Theapproach used is to split the output capacitance into twoparts: an inherent output capacitance CX of the driverstage and a load capacitance CY of the driven stage. Thelogic-level value of the capacitance is CX+ CY.The logic-level delay is given as()c,+ Cy Cx-Ti =~+1 7==: (9)g–yPwherec,‘= CX+CY”(lo)The optimum ~f for minimum delay for an FT buffer [61can be obtained fromPf[ln(Df)-l] = ~.(11)YFor a VT buffer, the delay of the k th stage is given as~~= p:(k+ 1)/zCX+ ~~,k+l)(k+WzC@(k+Wzgy =[l+(B$+’-1)P]T,.(12)The delay of the buffer is given asn—1[D.(B; -l)1Too= ~ (l+(@+l-l)P)Ti= n(l–p)+ ~ _l p ~i.k=Ou(13)The expression
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