1EE141MemoryEE141- Fall 2003Lecture 27EE141Announcements! Midterm2 returned today! Homework 10 due today! Remember: project presentations next Th2EE141Today’s Lecture! Finish with impact of interconnects! MemoryEE141Midterm 2 Statistics (67 Students)0611192470510152025300 6 12 18 24 30 36Total Score (Out of 36)Number of Studentsmean = 22.43median = 23.50std. dev = 6.61min = 6.5max = 333EE141Problem-3 was the Easiest0510152025300 20406080100Relative Score (%)Number of Studentsprob-1prob-2prob-3EE141TheMostCommonMistakes! Problem-1 (Logical effort)» Cin not equal for all inputs» Logical effort calculation for dynamic gate! Problem-2 (Pass-transistor logic)» Energy calculation» 4-way multiplexer implementation! Problem-3 (Pipelined adder) issues» Calculating min Tclk» Correctly pipelining the design4EE141Common Project-2 Questions! Account for delay in control logic orassume available control signals?! Include set-up time for dividend anddivisor in overall divider delay?! Average input-vector analysis or theworst-case input-vector analysis (theworst-case matters for min TClk)?! Account for “ill-conditioned” cases wherereminder needs one more restoration?EE141INTERCONNECTDealing with Inductance5EE141Ldi/dtCLV’DDVDDLi(t)VoutVinGND’LImpact of inductanceon supply voltages:• Change in current inducesthe change in voltage• Longer supply lines havelarger LEE141L di/dt: SimulationtttvoutiLvL20mA40mA5V0.2V0.01.02.03.04.05.0Vout(V)01020IL(mA)246810t(nsec)-0.3-0.10.10.30.5VL(V)tfall= 0.5 nsectfall=4nsecSignals Waveforms for Output Driver connected To Bonding Pads(a) vout;(b)iLand (c) vL.The Results of an Actual Simulation are Shown on the Right Side.6EE141Choosing the Right PinChipLL´Bonding wireMountingcavityLeadframePinEE141Decoupling CapacitorsSUPPLYBoardwiringBondingwireDecouplingcapacitorCHIPCd⫹⫺Decoupling capacitors are added:• on the board (right under the supply pins)• on the chip (under the supply straps, near large buffers)7EE141De-coupling Capacitor Ratios! EV4» total effective switching capacitance = 12.5nF» 128nF of de-coupling capacitance» de-coupling/switching capacitance ~ 10x! EV5» 13.9nF of switching capacitance» 160nF of de-coupling capacitance! EV6» 34nF of effective switching capacitance» 320nF of de-coupling capacitance -- not enough!Source: B. Herrick (Compaq)EE141EV6 De-coupling CapacitanceDesign for ∆Idd= 25 A @ Vdd = 2.2 V, f = 600MHz» 0.32-µF of on-chip de-coupling capacitance wasadded– Under major busses and around major gridded clock drivers– Occupies 15-20% of die area» 1-µF 2-cm2Wirebond Attached Chip Capacitor(WACC) significantly increases “Near-Chip” de-coupling– 160 Vdd/Vss bondwire pairs on the WACC minimizeinductanceSource: B. Herrick (Compaq)8EE141EV6 WACC587 IPGAMicroprocessorWACCHeat Slug389 Signal - 198 VDD/VSS Pins389 Signal Bondwires395 VDD/VSS Bondwires320 VDD/VSS BondwiresSource: B. Herrick (Compaq)EE141Design Techniques to address L di/dt! Separate power pins for I/O pads and chip core! Multiple power and ground pins! Position of power and ground pins on package! Increase tr and tf! Advanced packaging technologies! Decoupling capacitances on chip and on board9EE141MemoryEE141Issues in Memory" Memory Classification" Memory Architectures" The Memory Core" Periphery" Reliability" Case Studies10EE141Semiconductor MemoryClassificationRead-Write MemoryNon-VolatileRead-WriteMemoryRead-Only MemoryEPROME2PROMFLASHRandomAccessNon-RandomAccessSRAMDRAMMask-ProgrammedProgrammable (PROM)FIFOShift RegisterCAMLIFOEE141Memory Timing: DefinitionsWrite cycleRead access Read accessRead cycleWrite accessData writtenData validDATAWRITEREAD11EE141Memory Architecture: DecodersWord 0Word 1Word 2WordN⫺2WordN⫺1StoragecellMbitsMbitsNwordsS0S1S2SN⫺2A0A1AK⫺1K⫽log2NSN⫺1Word 0Word 1Word 2WordN⫺2WordN⫺1StoragecellS0Input-Output(Mbits)Intuitive architecture for N x M memoryToo many select signals:N words == N select signalsK=log2NDecoder reduces the number of select signalsInput-Output(Mbits)DecoderEE141Row DecoderBit line2L⫺KWord lineAKAK⫹1AL⫺1A0M.2KAK⫺1Sense amplifiers / DriversColumn decoderInput-Output(M bits)Storage cellArray-Structured Memory ArchitectureProblem: ASPECT RATIO or HEIGHT >> WIDTHAmplify swing torail-to-rail amplitudeSelects appropriateword12EE141Hierarchical Memory ArchitectureAdvantages:Advantages:1. Shorter wires within blocks1. Shorter wires within blocks2. Block address activates only 1 block => power savings2. Block address activates only 1 block => power savingsGlobalamplifier/driverControlcircuitryGlobal data busBlock selectorBlock 0RowaddressColumnaddressBlockaddressBlock i BlockP⫺ 1I/OEE141Block Diagram of 4 Mbit SRAMSubglobalrowdecoderGlobalrowdecoderSubglobalrowdecoderBlock30Block31128KArrayBlock0Block1ClockgeneratorCS, WEbufferI/ObufferY-addressbufferX-addressbufferx1/x4controllerZ-addressbufferX-addressbufferPredecoder and block selectorBit line loadTransfer gateColumn decoderSense amplifier and write driverLocalrowdecoder[Hirose90]13© Digital Integrated Circuits2ndMemoriesReadRead--Only Memory CellsOnly Memory CellsWLBLWLBL1WLBLWLBLWLBL0VDDWLBLGNDDiode ROM MOS ROM 1 MOS ROM 2© Digital Integrated Circuits2ndMemoriesMOS OR ROMMOS OR ROMWL[0]VDDBL[0]WL[1]WL[2]WL[3]VbiasBL[1]Pull-down loadsBL[2] BL[3]VDD14© Digital Integrated Circuits2ndMemoriesMOS NOR ROMMOS NOR ROMWL[0]GNDBL[0]WL[1]WL[2]WL[3]VDDBL[1]Pull-up devicesBL[2] BL[3]GND© Digital Integrated Circuits2ndMemoriesMOS NOR ROM LayoutMOS NOR ROM LayoutProgrammming using theActive Layer OnlyPolysiliconMetal1DiffusionMetal1 on DiffusionCell (9.5λ x7λ)15© Digital Integrated Circuits2ndMemoriesMOS NOR ROM LayoutMOS NOR ROM LayoutPolysiliconMetal1DiffusionMetal1 on DiffusionCell (11λ x7λ)Programmming usingthe Contact Layer Only© Digital Integrated Circuits2ndMemoriesMOS NAND ROMMOS NAND ROMAll word lines high by default with exception of selected rowWL[0]WL[1]WL[2]WL[3]VDDPull-up devicesBL[3]BL[2]BL[1]BL[0]16© Digital Integrated Circuits2ndMemoriesMOS NAND ROM LayoutMOS NAND ROM LayoutNo contact to VDD or GND necessary;Loss in performance compared to NOR ROMdrastically reduced cell sizePolysiliconDiffusionMetal1 on DiffusionCell (8λ x7λ)Programmming usingthe Metal-1 Layer Only© Digital Integrated Circuits2ndMemoriesNAND ROM LayoutNAND ROM LayoutCell (5λ x6λ)PolysiliconThreshold-alteringimplantMetal1 on DiffusionProgrammming usingImplants Only17© Digital Integrated Circuits2ndMemoriesEquivalent Transient Model
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