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Berkeley ELENG 141 - Lecture 7 Gate Delay and Logical Effort

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EE1411EECS1411Lecture #7EE141EE141--Fall 2009Fall 2009Digital Integrated Digital Integrated CircuitsCircuitsLecture 7Lecture 7Gate Delay and Gate Delay and Logical EffortLogical EffortEE1412EECS1412Lecture #7AnnouncementsAnnouncements Lab #3 this Fri., next Mon. and Tues. Homework #3 due today Homework #4 due next ThursdayEE1413EECS1413Lecture #7Class MaterialClass Material Last lecture Inverter delay optimization Today’s lecture Gate delay and logical effort Reading (Chapter 6)EE1414EECS1414Lecture #7Complex Gate DelayComplex Gate Delay Use RC model to estimate delay:CLBRnARpBRpARnCintEE1415EECS1415Lecture #7Complex Gate Delay (2)Complex Gate Delay (2) What is the delay in this case?CLBRnARpBRpARnCintEE1416EECS1416Lecture #7Elmore DelayElmore Delay• “Elmore delay”: approximation for delay of arbitrary (complex) RC circuits• To find “Elmore time constant”:• For each capacitor, draw path of current from cap to input• Multiply C by sum of R’s on current path that are common with path from Vinto Vout• Add up RC products from all capacitorsEE1417EECS1417Lecture #7Elmore Delay (Formal Method)Elmore Delay (Formal Method)• Apply current I across C, measure Vout• Calculate Reff= Vout/I• Time constant due to that C is Reff*CEE1418EECS1418Lecture #7Simplified Model: Elmore DelaySimplified Model: Elmore DelayR1C1R2C2R3C3VoutIC1IC2IC3Vin()( )11 1 2 2 1 2 3 3ElmoreRCRRCRRRCτ=++ +++EE1419EECS1419Lecture #7Another Elmore Delay ExampleAnother Elmore Delay ExampleR1C1R2C2VoutVinR2C2Elmoreτ=EE14110EECS14110Lecture #7Another Example GateAnother Example GateEE14111EECS14111Lecture #7Gate SizingGate SizingCLBRnARpBRpARnCintBRpARpARnBRnCLCint22221144EE14112EECS14112Lecture #7Sizing ExampleSizing ExampleOUT = D + A • (B + C)DABCDABCEE14113EECS14113Lecture #7Logical Logical EffortEffortEE14114EECS14114Lecture #7Question #1Question #1 All of these are decoders Which one is “best”?EE14115EECS14115Lecture #7Question #2Question #2 Is it better to drive a big capacitive load directly with the NAND gate, or after some buffering? Method to answer both of these questions: Logical effort Extension of buffer sizing problemCLCLEE14116EECS14116Lecture #7Buffer Chain ReviewBuffer Chain Review()1Ninv iiDelay t fγ==+∑For given N: Ci+1/Ci= Ci/Ci-1To find N: Ci+1/Ci~ 4CL = CN+1In Out12 Nfi= Ci+1/CiC1C2CNEE14117EECS14117Lecture #7Delay Of NAND GateDelay Of NAND GatetpNAND= kRW(Cint+ CL)= k(Rsq,n*L/W)(WCdnand+ CL)= k(Rsq,n*L*Cgnand)(Cdnand/Cgnand+CL/(WCgnand))= k(Rsq,n*L*4*Cg)(3/2*γ+CL/(4WCg))= tinv(2γ+ (4/3)f)2222Cdnand= 6CDCgnand = 4CG = (4/3) CginvCD/CG= γEE14118EECS14118Lecture #7Delay Of NOR GateDelay Of NOR GatetpNAND= kR(Cint+ CL)= k(Rsq,n*L/W)(WCdnor+ CL)= k(Rsq,n*L*Cgnor)(Cdnor/Cgnor+CL/(WCgnor))= k(Rsq,n*L*5*Cg)(6/5*γ+CL/(5WCg))= tinv(2γ+ (5/3)f)1Cdnor= 6CDCgnor = 5CG = (5/3) CginvCD/CG= γ144EE14119EECS14119Lecture #7Logical EffortLogical EffortMeasure everything in units of tinv(divide by tinv):p – intrinsic delay (kγg) - gate parameter ≠ f(W)LE – logical effort (k) – gate parameter ≠ f(W)f – electrical effort (effective fanout)Normalize everything to an inverter:LEinv=1, pinv= γtpgate= tinv(p + LE·f)EE14120EECS14120Lecture #7Logical EffortLogical Effort()Linv gininvCDelay k tCtpLEfγ⎛⎞=⋅ +⎜⎟⎝⎠=+⋅Measure everything in units of tinv(divide by tinv):p – intrinsic delay (kγg) - gate parameter ≠ f(W)LE – logical effort (k) – gate parameter ≠ f(W)f – electrical effort (effective fanout)Normalize everything to an inverter:LEinv=1, pinv= γEE14121EECS14121Lecture #7Graphical ViewGraphical ViewFan-out (f)Normalized delay (d)t1 2 3 4 5 6 7 pINVtpNANDEE14122EECS14122Lecture #7Delay in a Logic GateDelay in a Logic GateGate delay:Delay = EF + p (measured in units of tinv)effective fanoutintrinsic delayEffective fanout:EF = LE flogical effortelectrical fanout = Cout/CinLogical effort is a function of topology, independent of sizingEffective fanout is a function of load/gate sizeEE14123EECS14123Lecture #7Logical EffortLogical Effort Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates Logical effort LE is defined as:  (Req,gateCin,gate)/(Req,invCin,inv) Easiest way to calculate (usually): – Size gate to deliver same current as an inverter, take ratio of gate input capacitance to inverter capacitance LE increases with gate complexityEE14124EECS14124Lecture #7Logical EffortLogical EffortCalculating LE by sizing for same drive strength:LE = 1LE = LE = BAABFVDDVDDABABFVDDAAF1222221144Inverter 2-input NAND 2-input NOREE14125EECS14125Lecture #7Logical Effort of GatesLogical Effort of GatesFan-out (f)Normalized delay (d)t1 2 3 4 5 6 7 pINVtpNANDLE=1p=γd=f+γLE=4/3p=2γd=(4/3)f+2γp = γ·Fan-in(for top input)EE14126EECS14126Lecture #7Gate Sizing ConventionGate Sizing Convention Need to set a convention: What does a gate of size ‘2’ mean? For an inverter it is clear: Cinv= 2, Rinv= ½ For a gate, two possibilities: Cgate= 2Cinv Rgate= Rinv/2 In my notes, size ≡ Cgate/Cinv Size 2 gate has twice the input capacitance of a unit inverterEE14127EECS14127Lecture #7Adding BranchingAdding BranchingBranching effort: ,,,L on path L off pathLon pathCCbC−−−+=CL,on_pathCL,off_pathEE14128EECS14128Lecture #7Multistage NetworksMultistage NetworksEffective fanout: EFi= LEifiPath electrical fanout: F = Cout/CinPath logical effort: ΠLE = LE1LE2…LENBranching effort: ΠB = b1b2…bNPath effort: PE = ΠLE ΠΒ FPath delay D = Σdi= Σpi+ ΣEFi()1NiiiiDelay p LE f==+⋅∑EE14129EECS14129Lecture #7Optimum Effort per StageOptimum Effort per StageNEF PE=When each stage bears the same effort:NEFPE=()1/11ˆNNNii i iiiDLEfpNPE p===+=⋅+∑∑Minimum path delayEffective fanouts: LE1f1= LE2f2= … = LENfNEE14130EECS14130Lecture #7Optimal Number of StagesOptimal Number of StagesFor a given load, and given input capacitance of the first gateFind optimal number of stages and optimal sizing1/ NiDNPE p=⋅ +∑ˆ1/ NEFPE=The ‘best effective fanout’Remember: we can always add inverters to the end of the chainis still around 4(3.6 with γ=1)EE14131EECS14131Lecture #7Example: Optimize PathExample: Optimize PathElectrical fanout, F =ΠLE = PE =EF/stage =a =b = c = 1abc5LE = 1f = aLE = 5/3f = b/aLE = 5/3f = c/bLE = 1f = 5/cEE14132EECS14132Lecture #7Example: Optimize PathExample: Optimize PathElectrical fanout, F = 5ΠLE =


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