1EE141Timing and ClocksEE141- Spring 2003Lecture 23EE141Announcementsz Hardware lab this weekz Project-2 will be launched next week2EE141Today’s Lecturez Sequential Circuits (Cont.)z TimingEE141Sequential Logic3EE141Sequential Circuits (Cont.)z Schmitt Triggerz Monostable Multivibratorsz Astable MultivibratorsEE141Schmitt TriggerIn OutVinVou tVOHVOLVM–VM+•VTC with hysteresis•Restores signal slopes4EE141Noise Suppression usinga Schmitt TriggerVint0VM−VM+tVoutt0 +tptEE141CMOS Schmitt TriggerMoves switching thresholdof the first inverter VinM2M1VDDXVoutM4M35EE141Schmitt TriggerSimulated VTC2.5VX(V)VM2VM1Vin(V)Voltage-transfer characteristicswith hysteresis.2.01.51.00.50.00.0 0.5 1.0 1.5 2.0 2.52.5Vx(V)k= 2k= 3k= 4k= 1Vin(V)2.01.51.00.50.00.0 0.5 1.0 1.5 2.0 2.5The effect of varying the width of thePMOS device M4. W(M4) = k*0.5µmEE141CMOS Schmitt Trigger (2)VDDVDDOutInM1M5M2XM3M4M66EE141Multivibrator CircuitsBistable MultivibratorMonostable MultivibratorAstable Multivibratorflip-flop, Schmitt Triggerone-shotoscillatorSRTEE141Transition-Triggered MonostableDELAYtdInOuttdDelay element controls the duration of the pulse.7EE141Monostable Trigger (RC-based)VDDInOutABCRInBOuttVMt2t1Trigger circuitWaveformsEE141Astable Multivibrators (Oscillators)012 N-1Ring Oscillatorsimulated response of a 5-stage oscillator0.00.00.51.01.52.02.5V1V3V53.020.50.5time (ns)Volts1.0 1.58EE141Voltage Controlled Oscillator (VCO)InVDDM3M1M2M4M5VDDM6Vcontr Current starved inverterIrefIrefSchmitt Triggerrestores signal slopes0.5 1.5 2.5Vcontr (V )0.0246tpH L (nsec)propagation delay as a functionof control voltageEE141Timing9EE141Outlinez Timing parametersz Clock nonidealities (skew and jitter)z Impact of Clk skew on timingz Impact of Clk jitter on timingz Flip-flop- vs. Latch-based timingz Clock distributionEE141Datapath and Timing ParametersR1DQCombinationalLogicInCLKtCLK1R2DQtCLK2tc − qtc − q, cdtsu, tholdtlogictlogic, cdR1 and R2 can be latches or flip-flops10EE141Latch ParametersDClkQDQClkTClk-QTHPWmTSUTD-QDelays can be different for rising and falling data transitionsEE141Flip-Flop ParametersDClkQDQClkTClk-QTHPWmTSUDelays can be different for rising and falling data transitions11EE141Timing Constraints (Cycle Time and Race Margin)R1DQCombinationalLogicInCLKtCLK1R2DQtCLK2tc − qtc − q, cdtsu, tholdtlogictlogic, cdCycle time: TClk> tc-q+ tlogic+ tsuRace margin: thold< tc-q,cd+ tlogic,cdEE141Outlinez Timing parametersz Clock nonidealities (skew and jitter)z Impact of Clk skew on timingz Impact of Clk jitter on timingz Flip-flop- vs. Latch-based timingz Clock distribution12EE141Clock Nonidealitiesz Clock skew» Spatial variation in temporally equivalent clock edges; deterministic + random, tSKz Clock jitter» Temporal variations in consecutive edges of the clock signal; modulation + random noise» Cycle-to-cycle (short-term) tJS» Long term tJLz Variation of the pulse width » for level sensitive clockingEE141Clock Skew and Jitterz Both skew and jitter affect the effective cycle timez Only skew affects the race marginClkClktSKtJS13EE141Clock Skew# of registersClk delayInsertion delayEarliest occurrenceof Clk edgeNominal – Tsk/2Latest occurrenceof Clk edgeNominal + Tsk/2TskMax Clk skewEE141Sources of Skew and Jitter243Power SupplyInterconnect5Temperature6Capacitive Load7Coupling to Adjacent Lines1Clock GenerationDevices14EE141Positive SkewCLK1CLK2TCLKδTCLK+δ+ thδ2143Launching edge arrives before the receiving edgeEE141Negative SkewCLK1CLK2TCLKδTCLK +δ2143Receiving edge arrives before the launching edge15EE141Positive and Negative SkewR1In(a) Positive skewCombinationalLogicDQtCLK1CLKdelaytCLK2R2DQCombinationalLogictCLK3R3•••DQdelayR1In(b) Negative skewCombinationalLogicDQtCLK1delaytCLK2R2DQCombinationalLogictCLK3R3•••DQdelay CLKEE141Outlinez Timing parametersz Clock nonidealities (skew and jitter)z Impact of Clk skew on timingz Impact of Clk jitter on timingz Flip-flop- vs. Latch-based timingz Clock distribution16EE141Timing ConstraintsR1DQCombinationalLogicInCLKtCLK1R2DQtCLK2tc − qtc − q, cdtsu, tholdtlogictlogic, cdCycle time: TClk> tc-q+ tlogic+ tsuRace margin: thold< tc-q,cd+ tlogic,cdEE141Impact of Clock Skew on Timing: Cycle Time (Long Path)ClkTClktsutc-qtlogicArrival of next cycleδtc-q+ tlogic+ tsu< TClk+ δTClk> tc-q+ tlogic+ tsu-δ17EE141Impact of Clock Skew on Timing: Race Margin (Short Path)Clktc-q,cdtlogic,cdData must not arrivebefore this timeClktholdδtc-q,cd+ tlogic,cd> thold+ δthold+ δ< tc-q,cd+ tlogic,cdEE141Impact of Clock Skew on TimingPositive skew improves performanceNegative skew improves race marginWorst-case |δ| really mattersTClk> tc-q+ tlogic+ tsu-δthold+ δ< tc-q,cd+ tlogic,cd18EE141How to counter Clock Skew?REGφREGφREGφ.REGφlogOutInClock DistributionPositive SkewNegative SkewEE141Outlinez Timing parametersz Clock nonidealities (skew and jitter)z Impact of Clk skew on timingz Impact of Clk jitter on timingz Flip-flop- vs. Latch-based timingz Clock distribution19EE141Impact of Clock JitterCLK-tji t te rTCLKtjitterCLK InCombinat ionalLogi c tc-q , tc-q, cdtlog ictlog ic, cdtsu, thol dREGStjitter123456EE141Impact of Clock Jitter on Timing: Cycle Time (Late-Early Problem)ClkTClktsutc-qtlogicLatest point of launchingEarliest arrivalof next cycletjittertc-q+ tlogic+ tsu< TClk–tjitter–tjitterTClk> tc-q+ tlogic+ tsu+ 2 tjitter20EE141Impact of Clock Jitter on TimingTClk> tc-q+ tlogic+ tsu+ 2 tjitterNegative impact on cycle timeNo direct effect on race immunity (same Clk edge)Jitter reduces performanceEE141Combined Impact of Clock Jitter and Skew21EE141Impact of Clock Skew and Jitter: Cycle Time (Late-Early Problem)ClkTClktsutc-qtlogicLatest point of launchingEarliest arrivalof next cycletjitter + δtc-q+ tlogic+ tsu< TClk–tjitter–tjitter+ δTClk> tc-q+ tlogic+ tsu-δ+ 2 tjitterEE141Impact of Clock Skew and Jitter: Race Margin (Early-Late Problem)Clktc-q,cdtlogic,cdEarliest point of launchingData must not arrivebefore this timeClktholdNominalclock edgetc-q,cd+ tlogic,cd–tjitter> thold+ tjitter+ δthold+ 2 tjitter+ δ< tc-q,cd+ tlogic,cdLatest arrivalof next cycletjitter + δ22EE141Combined Impact of Clock Skew and Jitter on TimingTClk> tc-q+ tlogic+ tsu-δ+ 2 tjitterthold+ 2 tjitter+ δ< tc-q,cd+ tlogic,cdz Cycle time» Positive skew improves performance» Negative skew reduces performance» Jitter reduces performancez Race» Skew reduces race margin» Jitter reduces acceptable skewEE141Outlinez Timing
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