1EE141 – Fall 2005Lecture 6MOS Capacitances,MOS Capacitances,Propagation DelayPropagation DelayEE141 2Important! Check course home page periodically for announcements Homework 2 is due TODAY by 5pm• In 240 Cory Homework 3 will be posted TODAY• Due Thursday Sep 22 by 5pm2EE141 3Today’s Lecture The MOS transistor characteristics for transient analysis Propagation delayEE141 4ReviewMOS Transistor ModelMOS Transistor ModelCMOS Inverter VTCCMOS Inverter VTC3EE141 5Important to Remember!0 0.5 1 1.5 2 2.500.511.522.5x 10-4VDS(V)ID(A)VelocitySaturationVDS= VGTVDSAT= VGTSaturationLinearVDS= VDSATLinearRelationshipQuadraticRelationshipEE141 6A Unified Model for Manual AnalysisBDGIDS()DSGTDVVVVLWkI ⋅+⋅−⋅⋅⋅=λ12'2minminfor VGT≤ 0: ID=0with Vmin= min (VGT, VDS, VDSAT)for VGT≥ 0:define VGT= VGS– VT4EE141 7VDSpIDpVGSp= -2.5VGSp= -1VDSpIDnVin= 0Vin= 1.5VoutIDnVin= 0Vin= 1.5VoutIDnPMOS Load LinesVin= VDD+ VGSpIDn= -IDpVout= VDD+ VDSpVin= VDD+ VGSpIDn= -IDpVout= VDD+ VDSp Coordinate transform: IDp(VDSp) → IDn(Vout)EE141 8IDnVoutVin = 2.5Vin = 2Vin = 1.5Vin = 0Vin = 0.5Vin = 1NMOSVin = 0Vin = 0.5Vin = 1Vin = 1.5Vin = 2Vin = 2.5Vin = 1Vin = 1.5PMOSCMOS Inverter Load Characteristics5EE141 9CMOS Inverter VTCVin0.5 1 1.5 2 2.5NMOS resPMOS offNMOS satPMOS satNMOS offPMOS resNMOS satPMOS resNMOS resPMOS sat0.511.522.5VoutEE141 10Inverter Gain0 0.5 1 1.5 2 2.5-18-16-14-12-10-8-6-4-20Vin (V)gainpnDSATppDSATnnMDVkVkVIgλλ−⋅+⋅⋅−=)(1)()2(1pnDSATnTnMVVVrgλλ−⋅−−+≈6EE141 11Gain as a function of VDD0 0.5 1 1.5 2 2. 500.511.522.5Vin (V)Vout(V)Vin(V)Vout(V)0 0.05 0.1 0.15 0.200.050.10.150.2Vin (V)Vout (V)Vin(V)Vout(V)Gain = -1EE141 12Impact of Process Variations0 0.5 1 1.5 2 2.500.511.522.5Vin(V)Vout(V)Good PMOSBad NMOSGood NMOSBad PMOSNominal “Good” means:• tox• L• W• Vth7EE141 13OutlineDynamic Operation of Dynamic Operation of MOS TransistorMOS Transistor• MOS Capacitances• Propagation DelayEE141 14DSGBCGDCGSCSBCDBCGBMOS Capacitances8EE141 15The Gate CapacitanceWLtCoxoxgateε=toxn+n+Cross sectionLGate oxidetoxn+n+Cross sectionLGate oxidexdxdLdPolysilicon gateTop viewGate-bulkoverlapSourcen+Drainn+WxdxdLdPolysilicon gateTop viewGate-bulkoverlapSourcen+Drainn+WEE141 16Gate CapacitanceSDGCGCSDGCGCSDGCGCCut-off Resistive SaturationMost important regions in digital design: saturation and cut-offTextbook: page 109CGCBCGCSCGCD9EE141 17Cgateas a function of VGS(with VDS= 0)Cgateas a function of the degree of saturationGate Capacitance01VDS /(VGS – VT)CGCCGCSCGCDWLCox2WLCox23WLCoxWLCox2WLCoxVGSCGCCGCS=CGCDCGCBEE141 18Measuring the Gate CapVGSI-1.5 -1 -0.5 0345678910x10-162Gate Capacitance (F)0.5 1 1.5 2-2Capacitance (F)VGS(V)10EE141 19Diffusion CapacitanceBottomSide wallSide wallChannelSourceChannel-stop implantSubstrateWNA+NALSNDxjCdiff= Cbottom+ Csw= Cj· AREA + Cjsw· PERIMETER= Cj·LSW + Cjsw(2LS+ W)EE141 20Junction CapacitancemDjjVCC)1(00φ−=m = 0.5: abrupt junctionm = 0.33: linear junction11EE141 21Linearizing the Junction Cap Replace non-linear capacitance bylarge-signal equivalent linear capacitancewhich displaces equal charge over voltage swing of interest0)()(jeqlowhighlowjhighjDjeqCKVVVQvQVQC ⋅=−−=∆∆=[]mlowmhighlowhighmeqVVmVVK−−−−−−⋅−−=10100)()()1()(φφφEE141 22CGDCGSCSBCDBCGBCgate= CGB+ CGS+ CGDCapacitive Device Model= CGCS+ CGSO= CGCD+ CGDO= CGCB= CdiffGSDB= Cdiff12EE141 23Capacitances in 0.25µm CMOS ProcessTextbook: page 112EE141 24.MODEL Parameters MOS1 .MODEL Modname NMOS/PMOS <VT0=VT0…>13EE141 25PolysiliconInOutMetal1VDDGNDPMOSNMOSTwo Inverters1.2µm=2λEE141 26VDDTwo Inverters (modern view)14EE141 27FanoutVoutVinCLSimplifiedModelM3M4M1M 2CwCg3Cdb1Cg4Vout2Cdb2VDDVDDVinVoutCgd12Computing the CapacitancesEE141 28The CMOS Inverter: CinCgdn,pCgspCgsnSGDSVoutVinCinCL15EE141 29Miller EffectVoutVinZLZFAi1AVoutVini1Z1Z2ZLi1 =Vin (1-A)ZFi1 =VinZ1EE141 30Miller EffectZFAAZ1Z2Z1 =ZF1−AZ2 =ZF1A1−C1= CF·(1−A) C1= CF·(1−1/A)16EE141 31CMOS Inverter Example: CinCgdCgspCgsnCinA = -1Cgs = Cgsn + CgspCgd = Cgdn + CgdpCin= Cgs+ Cgd(1-A)+∆V-∆VEE141 32VinM1Cgd1Vout∆V∆VVinM1Vout∆V∆V2Cgd1The Miller Effect“A capacitor experiencing identical but opposite voltage swingat both terminals can be replaced by a capacitor to ground,whose value is two times the original value”2Cgd117EE141 33FanoutVoutVinCLSimplifiedModelM3M4M1M 2CwCg3Cdb1Cg4Vout2Cdb2VDDVDDVinVoutCgd12Computing the CapacitancesEE141 34Computing the Capacitances18EE141 35OutlineDynamic Operation of Dynamic Operation of MOS TransistorMOS Transistor• MOS Capacitances• Propagation DelayEE141 36CMOS Inverter Propagation Delay: Approach 1VoutIavgVDDVin=VDDCLavgswingLpHLIVCt2⋅=DDnLpHLVkCt⋅~19EE141 37CMOS Inverter Propagation Delay: Approach 2VoutRnVDDVin=VDDCL)(LonpHLCRft⋅=LonCR⋅=69.00.360.51RonCLtVoutln(0.5)VDDEE141 38MOS Transistor as a SwitchTraversed pathIDVDSVDDVDD /2VGS = VDDRmidR0∫∫⋅−=⋅−===212121)()(1)(1))((1212ttDDSttontttoneqdttItVttdttRtttRavgR())()(2121tRtRRononeq+⋅≈VGS≥ VTSDRon20EE141 39The Transistor as a SwitchVGS≥ VTSDRon()()⋅+⋅+⋅+⋅⋅=212121DDDSATDDDDDSATDDeqVIVVIVRλλ⋅⋅−⋅≈DDDSATDDeqVIVRλ65143IDVDSVDDVDD /2VGS = VDDRmidR0()021RRRmideq+⋅=EE141 400 0.5 1 1.5 2 2.5x 10-10-0.500.511.522.53t (sec)Vout(V)tp= 0.69 CL·(Reqn+Reqp)/2?tpLHtpHLTransient Response21EE141 41Design for Performance Keep capacitances small Increase transistor sizes• watch out for self-loading! Increase VDD(?)EE141 420.8 1 1.2 1.4 1.6 1.8 2 2.2 2.411.522.533.544.555.5VDD(V)tp(normalized)Delay as a function of VDD)2(')(52.04369.0DSATnTnDDDSATnnnDDLDSATnDDLpHLVVVVkLWVCIVCt−−⋅⋅⋅⋅=⋅=Req22EE141 432 4 6 8 10 12 1422.22.42.62.833.23.43.63.8x 10-11Stp(sec)Device Sizing(fixed load)Self-loading effect:Intrinsic capacitancesdominateEE141 441 1.5 2 2.5 3 3.5 4 4.5 533.544.55x 10-11βtp(sec)NMOS/PMOS RatiotpLHtpHLtpβ = Wp/Wn23EE141 45tpHL(nsec)0.350.30.250.20.15trise (nsec)10.80.60.40.20tp= tstep(i)+ η·tstep(i-1)Impact of Rise Time on DelayEE141 46 Threshold Variations Sub-threshold Conduction Parasitic ResistancesThe Sub-Micron MOS Transistor24EE141 47VTLLong-channel thresholdThreshold as a function ofchannel length (for low VDS) VDSVTThreshold VariationsLow VDSthresholdDrain induced barrier lowering (DIBL) (for low L) EE141 48Sub-Threshold ConductionTypical values for
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