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Berkeley ELENG 141 - Lecture 2 Design Metrics

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EE1411EE141EE141--Spring 2008Spring 2008Digital Integrated Digital Integrated CircuitsCircuitsCircuitsCircuitsLecture 2Lecture 2EE141EECS1411Lecture #2Design MetricsDesign MetricsAdministrative StuffAdministrative Stuff Discussions start next week  Labs start in week 3 Homework #1 is due next Friday Everyone should have an EECS instructional accountUsecoryquasar pulsarEE141EECS1412Lecture #2Use cory, quasar, pulsarEE1412SPICE Syntax (hidden)SPICE Syntax (hidden)Simple RTL inverter.include '/home/ff/ee141/MODELS/npn.mod'* netlistVCC vcc 0 5VIN in 0 PULSE 0 5 2NS 2NS 2NS 30NS 60NSQ1 out base 0 NPNRB in base 10KRC vcc out 1K*extra control informationoptions post=2 nomodEE141EECS1413Lecture #2.options post=2 nomod.op* analysis.TRAN 1NS 30NS.DC VIN 0 5 .1.ENDLast LectureLast Lecture Last lecture Introduction, Moore’s law, future of ICs Today’s lecture Introduces basic metrics for design of integrated circuits – how to measure delay, power cost etcEE141EECS1414Lecture #2power, cost, etc.EE1413Challenges in Digital DesignChallenges in Digital Design∝DSM∝1/DSM“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation•Clock distribution“Macroscopic Issues”• Complexity• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability∝DSM∝1/DSMEE141EECS1415Lecture #2 Clock distribution.Everything Looks a Little Differenty• etc.…and There’s a Lot of Them!?Why Scaling?Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly Cost of a function decreases by 2x But … How to design chips with more and more functions?Design engineering population does not double everyEE141EECS1416Lecture #2Design engineering population does not double every two years… Hence, a need for more efficient design methods Exploit different levels of abstractionEE1414Design MetricsDesign Metrics How to evaluate performance of a di it l i it ( t bl k )?digital circuit (gate, block, …)? Cost Reliability Speed/Performance (delay, frequency)PowerEE141EECS1417Lecture #2PowerCost of Integrated CircuitsCost of Integrated Circuits NRE (non-recurrent engineering) costs - fixed Independent of volume (i.e., number of units made/sold) Examples: design time and effort, mask generation, equipment, etc. Recurrent costs - variableEE141EECS1418Lecture #2 proportional to volume Examples: silicon processing, packaging, test Most of these proportional to chip areaEE1415NRE Cost is IncreasingNRE Cost is IncreasingEE141EECS1419Lecture #2Productivity TrendsProductivity Trends1,000,00010,000,00010,000,000100,000,000Logic Tr./ChipTr./Staff Month.10,0001,000er Chip(M)10,000100,000Mo.1101001,00010,000100,000335355101001,00010,000100,0001,000,000xxxxxxx21%/Yr. compoundProductivity growth ratex58%/Yr. compoundedComplexity growth rate1001010.10.010.001Logic Transistor pe0.010.11101001,000Productivity(K) Trans./Staff -MComplexityEE141EECS14110Lecture #2200319811983198519871989199119931995199719992001200520072009Source: SematechComplexity outpaces design productivityCourtesy, ITRS RoadmapEE1416Total CostTotal Cost Cost per IClcost fixed IC percost variable IC percost += Variable costvolumeppEE141EECS14111Lecture #2yieldtest finalpackaging ofcost test die ofcost die ofcost cost variable++=Die CostDie CostSi l diWaferSingle dieyield die* waferper dies waferofcost die ofcost =EE141EECS14112Lecture #2From: http://www.amd.comEE1417Wafer sizeWafer sizeAMD AthlonEE141EECS14113Lecture #2From: http://www.sandpile.org8” (200mm)12” (300mm)12” (300mm)90nm CMOS90nm CMOS65nm CMOSYieldYield%100 waferper chips of number Total waferper chips good of No.×=Ycost Wafercost Die=yield Die waferper Diescost Die×=()area die2diameter waferarea diediameter/2 wafer waferper Dies2××π−×π=EE141EECS14114Lecture #2EE1418DefectsDefectsYield = 1/4Yield = 19/24defects per unit area die areadie yield 1 ,α−×⎛⎞=+⎜⎟where αis approximately 3 EE141EECS14115Lecture #2die yield 1 ,α+⎜⎟⎝⎠where αis approximately 3 ()()4-1 -31die cost die areadie/wafer die area yield die area∝∝⎡⎤∝∝⎣⎦Cost per TransistorCost per Transistorcost:cost:0.000010.000010.00010.00010.0010.0010.010.010.10.111cost: cost: ¢¢--perper--transistortransistorFabrication cost per transistorEE141EECS14116Lecture #20.00000010.00000010.0000010.0000010.000010.0000119821982 19851985 19881988 199119911994199419971997 20002000 20032003 20062006 20092009 20122012EE1419ReliabilityReliability The real world is analog All physical quantities you deal with as a circuit designer are actually continuous Thus, even a “digital” signal can be noisy:i(t)v(t)VDDEE141EECS14117Lecture #2Inductive coupling Capacitive coupling Power and groundnoiseNoise and Digital SystemsNoise and Digital Systems Circuit needs to works despite “analog” noise Digital gates can reject noise This is actually how digital systems are defined Digital system is one where: Discrete values mapped to analog levels and back All the elements (gates) can reject noise–For “small” amounts of noise, output noise is less than EE141EECS14118Lecture #2pinput noise Thus, for sufficiently “small” noise, the system acts as if it was noiselessEE14110Noise RejectionNoise Rejection To see if a gate rejects noise Look at its DC voltage transfer characteristic (VTC)S h th h i ti t tl 1 0GVoutVDDGain = 0See what happens when input is not exactly 1 or 0 Ideal digital gate: Noise needs to belarger than VDD/2 to have any effecton gate outputEE141EECS14119Lecture #2Gain = ∞VinVDD/2VDDGain = 0on gate outputMore Realistic VTCMore Realistic VTCV(out)VOH =f(VOL)VOHVOLVMfV(out)=V(in)Switching ThresholdVOH = f(VOL)VOL = f(VOH)VM = f(VM)EE141EECS14120Lecture #2V(in)OLVOHVOLNominal Voltage LevelsEE14111Voltage MappingVoltage MappingSlope=-1VVoutVOH“1”Slope 1Slope = -1VOHVILVIHUndefinedRegionEE141EECS14121Lecture #2VILVIHVinpVOL“0”VOLILDefinition of Noise MarginsDefinition of Noise MarginsNoise margin high:NM“1”VOHUndefinedRegionNoise margin high:NMH= VOH–VIHNoise margin low:NML= VIL–VOLNMLNMH“0”VOLVILVIHEE141EECS14122Lecture #2Gate OutputGate Input0(Stage M) (Stage M+1)EE14112Digital Gate


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Berkeley ELENG 141 - Lecture 2 Design Metrics

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