EE1411EE1411EE141-S04EE141EE141--Spring 2004Spring 2004Digital Integrated Digital Integrated CircuitsCircuitsLecture 25Lecture 25Oscillators and BiOscillators and Bi--stablesstablesEE1412EE141-S04Administrative StuffAdministrative Stuff Homework 8 posted – Due on Fr Last software lab THIS week Project on web-site! No class on Th – Make-up lecture probably next week FrEE1412EE1413EE141-S04Class MaterialClass Material Today’s lecture Oscillators and multivibrators TimingEE1414EE141-S04Other Sequential CircuitsOther Sequential Circuits Schmitt Trigger Monostable Multivibrators Astable MultivibratorsEE1413EE1415EE141-S04Schmitt TriggerSchmitt TriggerIn OutVinVoutVOHVOLVM–VM+•VTC with hysteresis•Restores signal slopesEE1416EE141-S04Noise Suppression usingNoise Suppression usingSchmitt TriggerSchmitt TriggerEE1414EE1417EE141-S04CMOS Schmitt TriggerCMOS Schmitt TriggerMoves switching thresholdof the first inverter VinM2M1VDDXVoutM4M3EE1418EE141-S04Schmitt TriggerSchmitt TriggerSimulated VTCSimulated VTC2.5VX(V)VM2VM1Vin(V)Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of thePMOS device M4. The width is k* 0.5 m.m2.01.51.00.50.00.0 0.5 1.0 1.5 2.0 2.52.5Vx(V)k= 2k= 3k= 4k= 1Vin(V)2.01.51.00.50.00.0 0.5 1.0 1.5 2.0 2.5EE1415EE1419EE141-S04CMOS Schmitt Trigger (2)CMOS Schmitt Trigger (2)VDDVDDOutInM1M5M2XM3M4M6EE14110EE141-S04MultivibratorMultivibratorCircuitsCircuitsBistable MultivibratorMonostable MultivibratorAstable Multivibratorflip-flop, Schmitt Triggerone-shotoscillatorSRTEE1416EE14111EE141-S04TransitionTransition--Triggered Triggered MonostableMonostableDELAYtdInOuttdEE14112EE141-S04MonostableMonostableTrigger (RCTrigger (RC--based)based)VDDInOutABCRInBOuttVMt2t1(a) Trigger circuit.(b) Waveforms.EE1417EE14113EE141-S04AstableAstableMultivibratorsMultivibrators(Oscillators)(Oscillators)012 N-1Ring Oscillatorsimulated response of 5-stage oscillatorEE14114EE141-S04Relaxation OscillatorRelaxation OscillatorOut2CROut1IntI1I2T = 2 (log3) RCEE1418EE14115EE141-S04Voltage Controller Oscillator (VCO)Voltage Controller Oscillator (VCO)InVDDM3M1M2M4M5VDDM6Vcontr Current starved inverterIrefIrefSchmitt Triggerrestores signal slopes0.5 1.5 2.5Vcontr (V )0.0246tpHL (nsec)propagation delay as a functionof control voltageEE14116EE141-S04Timing Timing DefinitionsDefinitionsEE1419EE14117EE141-S04Synchronous TimingSynchronous TimingCombinationalLogicR1R2CinCoutOutInCLKEE14118EE141-S04Latch ParametersLatch ParametersDClkQDQClktc-qtholdPWmtsutd-qDelays can be different for rising and falling data transitionsTEE14110EE14119EE141-S04Register ParametersRegister ParametersDClkQDQClktc-qtholdTtsuDelays can be different for rising and falling data transitionsEE14120EE141-S04Clock UncertaintiesClock UncertaintiesSources of clock uncertainty243Power SupplyInterconnect5Temperature6Capacitive Load7Coupling to Adjacent Lines1Clock GenerationDevicesEE14111EE14121EE141-S04Clock Clock NonidealitiesNonidealities Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, tSK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL Variation of the pulse width Important for level sensitive clockingEE14122EE141-S04Clock Skew and JitterClock Skew and Jitter Both skew and jitter affect the effective cycle time Only skew affects the race marginClkClktSKtJSEE14112EE14123EE141-S04Clock SkewClock Skew# of registersClk delayInsertion delayMax Clk skewEarliest occurrenceof Clk edgeNominal –δ/2Latest occurrenceof Clk edgeNominal + δ/2δEE14124EE141-S04Positive and Negative SkewPositive and Negative SkewR1In(a) Positive skewCombinationalLogicDQtCLK1CLKdelaytCLK2R2DQCombinationalLogictCLK3R3•••DQdelayR1In(b) Negative skewCombinationalLogicDQtCLK1delaytCLK2R2DQCombinationalLogictCLK3R3•••DQdelayCLKEE14113EE14125EE141-S04Positive SkewPositive SkewLaunching edge arrives before the receiving edgeCLK1CLK2TCLKδTCLK+δ+thδ2143EE14126EE141-S04Negative SkewNegative SkewReceiving edge arrives before the launching edgeCLK1CLK2TCLKδTCLK+δ2143EE14114EE14127EE141-S04Timing ConstraintsTiming ConstraintsMinimum cycle time:T + δ= tc-q+ tlogic+ tsuWorst case is when receiving edge arrives early (negative δ)R1DQCombinationalLogicInCLKtCLK1R2DQtCLK2tc−qtc−q, cdtsu,tholdtlogictlogic, cdEE14128EE141-S04Timing ConstraintsTiming ConstraintsHold time constraint:t(c-q, cd)+ t(logic, cd)> thold+ δWorst case is when receiving edge arrives late (positive δ)Race between data and clockR1DQCombinationalLogicInCLKtCLK1R2DQtCLK2tc−qtc−q, cdtsu,tholdtlogictlogic, cdEE14115EE14129EE141-S04Impact of JitterImpact of JitterCLK-tjitterTCLKtjitterCLK InCombinationalLogic tc-q , tc-q, cdtlogictlog ic, cdtsu, tholdREGStjitter123456EE14130EE141-S04Longest Logic Path in Longest Logic Path in EdgeEdge--Triggered SystemsTriggered SystemsClkTTSUTClk-QTLMLatest point of launchingEarliest arrivalof next cycleTJI + δEE14116EE14131EE141-S04Clock Constraints in Clock Constraints in EdgeEdge--Triggered SystemsTriggered SystemsIf launching edge is late and receiving edge is early, the data will not be too late if:Minimum cycle time is determined by the maximum delays through the logicTc-q+ TLM+ TSU< T – TJI,1–TJI,2-δTc-q+ TLM+ TSU+ δ+ 2 TJI< TSkew can be either positive or negativeEE14132EE141-S04Shortest PathShortest PathClkTClk-QTLmEarliest point of launchingData must not arrivebefore this timeClkTHNominalclock edgeEE14117EE14133EE141-S04Clock Constraints Clock Constraints in Edgein Edge--Triggered SystemsTriggered SystemsMinimum logic delay If launching edge is early and receiving edge is late:Tc-q+ TLM–TJI,1< TH+ TJI,2+ δTc-q+ TLM< TH+ 2TJI+ δEE14134EE141-S04How to counter Clock Skew?How to counter Clock Skew?REGφREGφREGφ.REGφlogOutInClock DistributionPositive SkewNegative SkewData and Clock RoutingEE14118EE14135EE141-S04Clock DistributionClock DistributionClock is distributed in a tree-like fashionH-treeCLKEE14136EE141-S04More realistic HMore realistic H--treetree[Restle98]EE14119EE14137EE141-S04The Grid SystemThe Grid SystemDriverDriverDr iv erDr iverGCLKGCLKGCLKGCLK•No rc-matching•Large powerEE14138EE141-S04Example: DEC Alpha 21164Example: DEC Alpha 21164Clock Frequency: 300 MHz - 9.3 Million TransistorsTotal Clock Load: 3.75 nFPower in Clock Distribution network : 20 W (out of 50)Uses Two Level
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