1EE1411EE141MetricsCMOS InverterMOS Transistor ModelEE141EE141--Spring 2004Spring 2004Lecture 4Lecture 4EE1412EE141Today’s lectureToday’s lecture Design Metrics (continued) The CMOS inverter at a glance An MOS transistor model for manual analysis2EE1413EE141Important!Important! Labs start next week You must show up in one of the lab sessions If you don’t show up you will be dropped from the class Unless you let me know that you still want to be in the class Homework 2 will be posted later today. Due next Thursday, February 6.EE1414EE141The Ideal GateThe Ideal GateRi = ∞Ro = 0Fanout = ∞NMH= NML= VDD/2g = ∞VinVout3EE1415EE141An OldAn Old--time Invertertime InverterNMHVin(V)Vout(V)NMLVM0.01.02.03.04.05.01.0 2.0 3.0 4.0 5.0EE1416EE141Example: An OldExample: An Old--time Invertertime Inverter VOH= 3.6V VOL= 0.4V VIL= 0.6V VIH= 2.3V NMH= VOH– VIH= 1.3V NML= VIL– VOL= 0.2V4EE1417EE141Delay DefinitionsDelay DefinitionsVouttftpHLtpLHtrtVint90%10%50%50%EE1418EE141Ring OscillatorRing Oscillatorv0v1v5v1v2v0v3v4v5T = 2 ×tp×N5EE1419EE141A FirstA First--Order RC NetworkOrder RC NetworkvoutvinCRtp= ln (2) τ = 0.69 RCImportant model – matches delay of an inverterEE14110EE141Power DissipationPower DissipationInstantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)Peak power: Ppeak= VsupplyipeakAverage power: ()∫∫++==TttTttsupplysupplyavedttiTVdttpTP )(16EE14111EE141Energy and EnergyEnergy and Energy--DelayDelayPower-Delay Product (PDP) =E = Energy per operation = Pav×tpEnergy-Delay Product (EDP) =quality metric of gate = E ×tpEE14112EE141A FirstA First--Order RC NetworkOrder RC NetworkvoutvinCLR() ()∫∫∫====→DDVDDLoutLDDTTDDDDDDVCdvCVdttiVdttPE020010() ()∫∫∫====DDVDDLoutoutLTTLoutCCVCdvvCdttivdttPE0200217EE14113EE141SummarySummary Understanding the design metrics that govern digital design is crucial Cost Robustness Speed Power and energy dissipationEE14114EE141CMOS InverterCMOS InverterMOS TransistorMOS Transistor8EE14115EE141What is a Transistor?What is a Transistor?VGS ≥ VTRonSDA Switch!|VGS|A MOS TransistorEE14116EE141NMOS and PMOSNMOS and PMOSVGS<0PMOS TransistorVGS>0NMOS TransistorSDGSDG9EE14117EE141CMOS Inverter: First GlanceCMOS Inverter: First GlancePolysiliconInOutVDDGNDPMOS2λMetal 1NMOSOutInVDDPMOSNMOSContactsN WellEE14118EE141CMOS InverterCMOS InverterFirstFirst--Order DC AnalysisOrder DC AnalysisVOL= 0VOH= VDDVM= f(Rn, Rp)VDDVDDVin⫽VDDVin⫽0VoutVoutRnRp10EE14119EE141CMOS Inverter: Transient ResponseCMOS Inverter: Transient ResponsetpHL= f(Ron.CL)= 0.69 RonCLVoutVoutRnRpVDDVDDVin⫽VDDVin⫽0(a) Low-to-high (b) High-to-lowCLCLEE14120EE141CMOS PropertiesCMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power dissipation Direct path current during switching11EE14121EE141MOS Transistors MOS Transistors --Types and SymbolsTypes and SymbolsDSGDSGGSDDSGNMOSEnhancementNMOSPMOSDepletionEnhancementBNMOS withBulk ContactEE14122EE141Threshold Voltage: ConceptThreshold Voltage: Conceptn+p-substrateDSGBVGS+–Depletionregionn-channeln+12EE14123EE141The Threshold VoltageThe Threshold VoltageThresholdFermi potential2φFis approximately - 0.6V for p-type substratesγ –the body factorVT0is approximately 0.45V for our processEE14124EE141The Body EffectThe Body Effect-2.5 -2 -1.5 -1 -0.5 00.40.450.50.550.60.650.70.750.80.850.9VBS (V)VT (V)13EE14125EE141The Drain CurrentThe Drain CurrentCharge in the channel is controlled by the gate voltage: Drain current is proportional to charge and velocity:EE14126EE141The Drain CurrentThe Drain CurrentCombining velocity and charge:Integrating over the channel:Transconductance:14EE14127EE141Transistor in LinearTransistor in Linearn+n+p-substrateDSGBVGSxLV(x)+–VDSIDMOS transistor and its bias conditionsLinear (Resistive) modeEE14128EE141Transistor in SaturationTransistor in Saturationn+n+SGVGSDVDS > VGS - VTVGS - VT+-Pinch-off15EE14129EE141SaturationSaturationFor VGD< VT, the drain current saturatesIncluding channel-length modulation()22TGSnDVVLWkI −′=()()DSTGSnDVVVLWkI λ+−′= 122EE14130EE141Modes of OperationModes of OperationCutoff:VGS< VTID= 0Resistive:VT< VGS ; VGS− VT> VDS()22TGSnDVVLWkI −′=Saturation:VT< VGS ; VGS− VT< VDS()⎥⎥⎦⎤⎢⎢⎣⎡−−′=222DSDSTGSnDVVVVLWkI16EE14131EE141CurrentCurrent--Voltage RelationsVoltage RelationsA Good A Good OlOl’ Transistor’ TransistorQuadraticRelationship0 0.5 1 1.5 2 2.50123456x 10-4VDS(V)ID(A)VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 VResistive SaturationVDS= VGS-VTEE14132EE141A model for manual analysisA model for manual analysis17EE14133EE141CurrentCurrent--Voltage RelationsVoltage RelationsThe DeepThe Deep--Submicron EraSubmicron EraLinearRelationship-4VDS(V)0 0.5 1 1.5 2 2.500.511.522.5x 10ID(A)VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 VEarly SaturationEE14134EE141Velocity SaturationVelocity Saturationξ(V/µm)ξc= 1.5υn(m/s)υsat= 105Constant mobility (slope = µ)Constant velocity18EE14135EE141Velocity SaturationVelocity SaturationIDLong-channel deviceShort-channel deviceVDSVDSATVGS-VTVGS = VDDEE14136EE141IIDDversus Vversus VGSGS0 0.5 1 1.5 2 2.50123456x 10-4VGS(V)ID(A)0 0.5 1 1.5 2 2.500.511.522.5x 10-4VGS(V)ID(A)quadraticquadraticlinearLong ChannelShort Channel19EE14137EE141IIDDversus Vversus VDSDS-4VDS(V)0 0.5 1 1.5 2 2.500.511.522.5x 10ID(A)VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 V0 0.5 1 1.5 2 2.50123456x 10-4VDS(V)ID(A)VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 VResistive SaturationVDS= VGS-VTLong Channel Short ChannelEE14138EE141Including Velocity SaturationIncluding Velocity SaturationApproximate velocity:And integrate current again:In deep submicron, there are four regions of operation:(1) cutoff, (2) resistive, (3) saturation and (4) velocity saturation20EE14139EE141Regions of OperationRegions of OperationLong Channel Short ChannelEE14140EE141An Unified ModelAn Unified Modelfor Manual Analysisfor Manual AnalysisSDGB21EE14141EE141Regions of OperationRegions of Operation0 0.5 1 1.5 2 2.500.511.522.5x 10-4DSV(V)ID(A)VelocitySaturatedLinearSaturatedVDSAT=VGTVDS=VDSATVDS=VGT0 0.5 1 1.5 2 2.500.511.522.5x 10-4DSV(V)DSV(V)ID(A)VelocitySaturatedLinearSaturatedVDSAT=VGTVDS=VDSATVDS=VGTEE14142EE141A PMOS TransistorA PMOS Transistor-2.5 -2 -1.5 -1 -0.5 0-1-0.8-0.6-0.4-0.20x 10-4VDS(V)ID(A)Assume all variablesnegative!VGS = -1.0VVGS = -1.5VVGS = -2.0VVGS = -2.5V22EE14143EE141Transistor
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