EE141EE141EECS1411Lecture #17EE141EE141--Spring 2008Spring 2008Digital Integrated Digital Integrated CircuitsCircuitsLecture 17Lecture 17Dynamic LogicDynamic LogicEE141EECS1412Lecture #17Administrative StuffAdministrative Stuff Project phase 1 due on We April 2!! Report template to be posted posted on the webEE141EE141EECS1413Lecture #17Class MaterialClass Material Last lecture Pass-transistor logic Today’s lecture Dynamic logic Reading Chapter 6EE141EECS1414Lecture #17Pass-Transistor Logic (Review)InputsSwitchNetworkOutOutABBB• N transistors• No static consumptionEE141EE141EECS1415Lecture #17NMOS-only ChallengeA = 2.5 VBC = 2.5VCLA = 2.5 VC = 2.5 VBM2M1MnThreshold voltage loss causesstatic power consumptionVBdoes not pull up to 2.5V, but 2.5V -VTNNMOS has higher threshold than PMOS (body effect)EE141EECS1416Lecture #17NMOS Only Logic: NMOS Only Logic: Level Restoring TransistorLevel Restoring TransistorM2M1MnMrOutABVDDVDDLevel RestorerX• Advantage: Full Swing• Restorer adds capacitance, takes away pull down current at X• Ratio problemEE141EE141EECS1417Lecture #17Complementary Pass Transistor LogicComplementary Pass Transistor LogicABABBBB BABABF=ABF=ABF=A+BF=A+BB BAAAAF=A⊕ΒÝF=A⊕ΒÝOR/NOREXOR/NEXORAND/NANDFFPass-TransistorNetworkPass-TransistorNetworkAABBAABBInverse(a)(b)EE141EECS1418Lecture #17CPL Level RestoreCPL Level RestoreEE141EE141EECS1419Lecture #17Solution 2: Transmission GateABCCABCCBCLC = 0 VA = 2.5 VC = 2.5 VEE141EECS14110Lecture #17Resistance of Transmission GateResistance of Transmission GateVout0 V2.5 V2.5 VRnRp0. 0 1. 0 2 .00 10 20 30 Vou t, VResistance, ohmsRnRpRn || RpEE141EE141EECS14111Lecture #17LE with Transmission GatesLE with Transmission GatesEE141EECS14112Lecture #17PassPass--Transistor Based MultiplexerTransistor Based MultiplexerAM2M1BSSSFVDDGNDVDDIn1In2SSSSEE141EE141EECS14113Lecture #17Transmission Gate XORTransmission Gate XOREE141EECS14114Lecture #17Delay in Transmission Gate NetworksV1 Vi-1C2.52.500Vi Vi+1CC2.50Vn-1 VnCC2.50InV1ViVi+1CVn-1VnCCInReqReqReqReqCC(a)(b)CReqReqCCReqCCReqReqC CReqCInm(c)EE141EE141EECS14115Lecture #17Delay OptimizationDelay OptimizationEE141EECS14116Lecture #17Transmission Gate Full AdderTransmission Gate Full AdderABPCiVDDAAAVDDCiAPABVDDVDDCiCiCoSCiPPPPPSum GenerationCarry GenerationSetupSimilar delays for sum and carryEE141EE141EECS14117Lecture #17Dynamic LogicDynamic LogicEE141EECS14118Lecture #17Dynamic CMOSDynamic CMOS In static circuits, at every point in time (except when switching) the output is connected to either GND or VDDvia a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. only requires n + 2 (n+1 N-type + 1 P-type) transistorsEE141EE141EECS14119Lecture #17Dynamic GateDynamic GateIn1In2PDNIn3MeMpClkClkOutCLOutClkClkABCMpMeTwo phase operationPrecharge (Clk = 0)Evaluate (Clk = 1)onoff1offon((AB)+C)EE141EECS14120Lecture #17Conditions on OutputConditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CLEE141EE141EECS14121Lecture #17Properties of Dynamic GatesProperties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL= GND and VOH= VDD) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced capacitance due to lower input capacitance (Cin) no Isc, so all the current provided by PDN goes into discharging CLEE141EECS14122Lecture #17LE of Dynamic GatesLE of Dynamic GatesInClkClkOutCLCgate=LE = AClkClkOutCLBCgate=LE =EE141EE141EECS14123Lecture #17Properties of Dynamic GatesProperties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between VDDand GND (including Psc) no glitching higher transition probabilities extra load on Clk PDN starts to work as soon as the input signals exceed VTn, so VM, VIHand VILequal to VTn low noise margin (NML) Needs a precharge/evaluate clockEE141EECS14124Lecture #17Issues in Dynamic Design 1: Issues in Dynamic Design 1: Charge LeakageCharge LeakageCLClkClkOutAMpMeLeakage sourcesCLKVOutPrechargeEvaluateDominant component is subthreshold currentEE141EE141EECS14125Lecture #17Solution to Charge LeakageSolution to Charge LeakageCLClkClkMeMpABOutMkpSame approach as level restorer for pass-transistor logicKeeperEE141EECS14126Lecture #17Dynamic Gate VTCDynamic Gate VTCCLClkClkMeMpAOutMkpOutEE141EE141EECS14127Lecture #17Issues in Dynamic Design 2: Issues in Dynamic Design 2: Charge SharingCharge SharingCLClkClkCACBB=0AOutMpMe Charge initially stored on CL CApreviously discharged When A rises, this charge is redistributed (shared) between CLand CA Makes Out drop below VDDEE141EECS14128Lecture #17Charge Sharing ExampleCharge Sharing ExampleEE141EE141EECS14129Lecture #17Charge SharingCharge SharingB=0ClkXCLCaCbAOutMpMaVDDMbClkMe• Two cases:•Mastays on – complete charge share•Maturns off – incomplete charge share•Complete charge share:•QCa= VOutCaΔQCL= -VOutCaÆ ΔVOut= -VDDCa/(Ca+CL)•Incomplete charge share:•QCa= (VDD-VTN*)CaΔQCL= -(VDD-VTN*)CaÆ ΔVOut= -(VDD-VTN*)Ca/CLEE141EECS14130Lecture #17Solution to Charge SharingSolution to Charge SharingClkClkMeMpABOutMkpClk• Keeper helps a lot•Can still get failures if Out drops below inverter Vsw• Another option: precharge internal nodes•Increases power and areaEE141EE141EECS14131Lecture #17Issues in Dynamic Design 3: Clock Issues in Dynamic Design 3: Clock FeedthroughFeedthroughCLClkClkBAOutMpMeCoupling between Out and Clk input of the prechargedevice due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.EE141EECS14132Lecture #17Clock Clock FeedthroughFeedthrough-0.50.51.52.500.51ClkClkIn1In2In3In4OutIn &ClkOutTime, nsVoltageClock feedthroughClock feedthroughEE141EE141EECS14133Lecture #17Issues in Dynamic Design 4: Issues in Dynamic Design 4: BackgateBackgateCouplingCouplingCL1ClkClkB=0A=0Out1MpMeOut2CL2InDynamic NAND Static
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