EE1411EE141EE141--Spring 2008Spring 2008Digital Integrated Digital Integrated CircuitsCircuitsCircuitsCircuitsLecture 9Lecture 9EE141EECS1411Lecture #9Power + Buffer Power + Buffer SizingSizingAnnouncementsAnnouncements Lab 4 this week No lab next week Homework #4 due Mo March 3 Midterm 1 next Friday! No labs, no new homework next weekEE141EECS1412Lecture #9 Covers lectures 1-8EE1412Class MaterialClass Material Last lecture Inverter delay Power dissipation Today’s lecture Power Dissipation, Buffer sizingEE141EECS1413Lecture #9 Reading (5.4, 5.5)Review: Slope EffectReview: Slope Effect100psV*tp = ?CLTp,ramp p,step p,inDDV*tt tV=+⋅pt =EE141EECS1414Lecture #9EE1413Review: Slope EffectReview: Slope Effect1=pp,steptt2=+pp,stepttTp,stepDDV*tV⋅3=tEE141EECS1415Lecture #93pt4=ptSwitch Model for Delay and PowerSwitch Model for Delay and PowerEE141EECS1416Lecture #9EE1414Review: Dynamic PowerReview: Dynamic PowerEE141EECS1417Lecture #9Short Circuit CurrentShort Circuit CurrentVDDIsc∼ 0VDDIsc= IMAX11.522.5Isc (A)x 10−4CL = 20 fFCL = 100 fFC= 500 fFVinVoutCLVinVoutCLLarge loadSmall loadEE141EECS1418Lecture #9 Short circuit current usually well controlled0 20−0.500.540 60ICL= 500 fFtime (s)EE1415Diode LeakageDiode LeakageGATENp+p+Reverse Leakage Current+-VddEE141EECS1419Lecture #9JS = 10-100 pA/μm2 at 25 deg C for 0.25μm CMOSJS doubles for every 9 deg C!Much smaller than transistor leakage in deep submicronIDL= JS×ATransistor LeakageTransistor Leakage Transistors that are supposed to be off -leakVDD0VVDDILeakVDD0VVDDEE141EECS14110Lecture #9Input at VDDInput at 0ILeakEE1416Transistor LeakageTransistor Leakage-4-3VDS= 1.2VG-8-7-6-5log IDS [log A]GSDSubCiCdEE141EECS14111Lecture #911-90 0.2 0.4 0.6 0.8 1 1.2VGS [V]Drain leakage current is exponential with VGS-VTSubSub--Threshold ConductionThreshold Conduction10-2LiInverse Subthreshold Slope:()GS TqV VC−10-810-610-4ID(A)LinearEtilQuadratic()0~, 1DnkTDoxCIIe nC=+S-1is ΔVGSfor ID2/ID1=10-1EE141EECS14112Lecture #90 0.5 1 1.5 2 2.510-1210-10VGS(V)VTExponentialTypical values for S-1:60 .. 100 mV/decadeEE1417Review: Subthreshold SlopeReview: Subthreshold Slope• How much does Ileakchange if change VT?-1• So, if lowered VTby:EE141EECS14113Lecture #9Transistor LeakageTransistor Leakage3-10x in currenttechnologiesIDS[nA]()()01GS T DSDSqV V VqVnkT kTDIIe eη−−−⎛⎞=−⎜⎟⎝⎠EE141EECS14114Lecture #914Two effects:• diffusion current (like a bipolar transistor)• exponential increase with VDS(η: DIBL)00 0.2 0.4 0.6 0.8 1 1.2 1.4VdS[V]EE1418Review: DIBLReview: DIBL• Leakage set by VT•But VTchanges with VDSBut VTchanges with VDSEE141EECS14115Lecture #915Threshold VariationsThreshold VariationsVTVTLLong-channel thresholdLow VDSthresholdVDSEE141EECS14116Lecture #9LThreshold as a function of the length (for low VDS) Drain-induced barrier lowering (DIBL) (for short L)EE1419Sizing of an Sizing of an Inverter ChainInverter ChainEE141EECS14117Lecture #917Inverter ChainInverter ChainInOutCL For some given CL:How many stages are needed to minimize delay?EE141EECS14118Lecture #9How many stages are needed to minimize delay? How to size the inverters? Anyone want to guess the solution?EE14110Careful about Optimization Careful about Optimization ProblemsProblems Get fastest delay if build one very big inverterinverter So big that delay is set only by self-loadingEE141EECS14119Lecture #919 Likely not the problem you’re interested in Someone has to drive this inverter…Engineering Optimization Engineering Optimization Problems in GeneralProblems in General Need to have a set of constraints Constraints key to: Making the result useful Making the problem have a ‘clean’ solutionEE141EECS14120Lecture #9 For sizing problem: Need to constrain size of first inverterEE14111Delay Optimization Problem #1Delay Optimization Problem #1 You are given:Afixednumber of invertersA fixednumber of inverters The size of the first inverter The size of the load that needs to be driven Your goal:Minimize the delay of the inverter chainEE141EECS14121Lecture #9Minimize the delay of the inverter chain Need model for inverter delay vs. size2WInverter DelayInverter Delay Minimum length devices, L = 0.25μm Assume that for WP= 2WN= 2W same pull-up and pull-down currents,,Psqp Nsqn WPNLLRR RR RWW⎛⎞⎛⎞=≈==⎜⎟⎜⎟⎝⎠⎝⎠W approximately equal resistances, RN= RP approx. equal rise and fall delays, tpHL= tpLH Analyze as an RC networkEE141EECS14122Lecture #9tpHL= (ln 2) RNCL= tpLH= (ln 2) RpCLDelay (D):3in gCWC=Loading on the previous stage:EE14112CP= 2WCg2WInverter DelayInverter Delay,WsqnLRRW⎛⎞=⎜⎟⎝⎠CintCLCN= WCgWint3dCWC=3in gCWC=EE141EECS14123Lecture #9Replace ln(2) with k (a constant):Delay = kRWCint+ kRWCLDelay = kRsq,n(L/W)(3WCd) + kRsq,n(L/W)CLDelayCP= 2WCg2WInverter with LoadInverter with LoadLoadCintCLCN= WCgWEE141EECS14124Lecture #9Delay = kRW Cin(Cint/Cin+CL/Cin)= 3kLRsq,nCg[Cd/Cg + CL/(3WCg)]= Delay (Internal) + Delay (Load)EE14113()~Wint LDelay R C C+Delay FormulaDelay Formula()()in int/pW inLininvtkRCCCCC t fγ=+=+Cint= γCin(γ≈1 for inverter)f = CL/Cin– electrical fanoutRR(L/W)C3WCEE141EECS14125Lecture #925RW= Rsq(L/W);Cin=3WCgtinv= 3·ln(2)·L·RsqCgtinvis independent of sizing of the gate!!!In OutApply to Inverter ChainApply to Inverter ChainCL12 Ntp= tp1+ tp2+ …+ tpN,1in jpj invijCttCγ+⎛⎞=+⎜⎟⎜⎟⎝⎠EE141EECS14126Lecture #9,injC⎝⎠,1,,111,, NNin jppjinv inNLjiin jCttt CCCγ++==⎛⎞== + =⎜⎟⎜⎟⎝⎠∑∑EE14114Optimal Tapering for Given Optimal Tapering for Given NN Delay equation has N-1 unknowns, Cin,2… Cin,N,110pinjdt Ctt+=−= To minimize the delay, find N-1 partial derivatives:,,1,1 ,... ...in j in jpinv invin j in jCCtt tCC+−=+ + +EE141EECS14127Lecture #92,,1,0inv invin j in j in jttdC C C−Optimal Tapering for Given Optimal Tapering for Given NN(cont’d)(cont’d) Result: every stage has equal fanout: In other words, size of each stage is geometric mean of two neighbors:,,1,1 ,in j in jin j in jCCCC+−=EE141EECS14128Lecture #9,,1,1in j in j in jCCC−+= Equal fanout Æ every stage will have same delayEE14115Optimum Delay and Number of StagesOptimum Delay and Number of Stages When each stage has same fanout f :,1/NLinfFCC==NFf = Effective fanout of each stage:EE141EECS14129Lecture #9()NpinvtNt Fγ=+ Minimum path
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