1EE141 – Fall 2005Lecture 26Memory (Cont.)Memory (Cont.)PerspectivesPerspectivesEE141 2Administrative Stuff Homework 10 posted – just for practice• No need to turn in Office hours next week, schedule TBD. HKN review today. Your feedback is important! Final covers all material covered in class. Precise overview to be posted on web-site. Review session schedule TBD.2EE141 3Project 2 – Summary Variety of topologies and circuit styles• Most projects focused on mix of static logic families Some very impressive presentations• Refer to examples on web-site Grades• Mean: 79.3 • Median: 78.9 (3.868, static)• Sigma: 19• Max: 110 (0.944, dynamic; 1.316, static)EE141 4Sizing Optimization16XStage Z: LE=1 B=133.84u/1.92u960n960n2.88u/720n2.4u/1.2u0.96n0.96n1.2u 0.96n0.48u0.48u16XGin7Gin5Gin0 Gin1Gin2Gin3Gin4Gin6Pin7Pin1 Pin2Pin5Pin3Pin4Pin6Pin0AStage V: LE=1, B=1Stage W: LE=1, B=4Stage X : LE=4/3, B=1Stage Y: LE=2, B=1Area Concern0.96u/0.48u1638123411==××××=FOLE8.2416384:5/15/1=××=PEBranching00.1=v78.2=w08.4=y70.5=z94.1=xSize:2.542.5Manchester Sizing3EE141 5Layout Techniques Size : 1265.22 µm2(33.00µm x 38.34µm) Critical Path drawn in arrow Aspect Ratio = 1.162 Routing• Metal 1− Horizontal Line− VDD, GND• Metal 2:− Vertical Line• Metal 3:− Clock SignalsFA0 FA1 FA2 FA3FA7 FA6 FA5 FA4INPUT BUFFER INPUT BUFFERINPUT BUFFER INPUT BUFFEROUTPUTBUFFEROUTPUTBUFFEROUTPUTBUFFEROUTPUTBUFFERCLOCKCHAINMemoryMemory4EE141 7Read-Write MemoryNon-VolatileRead-WriteMemoryRead-Only MemoryEPROME2PROMFLASHRandomAccessNon-RandomAccessSRAM DRAMMask-ProgrammedProgrammable (PROM)FIFOShift RegisterCAMLIFOSemiconductor Memory ClassificationEE141 8Read-Only Memory CellsWLBLWLBL1WLBLWLBLWLBL0VDDWLBLGNDDiode ROMMOS ROM 1MOS ROM 25EE141 9WL[0]GNDBL [0]WL [1]WL [2]WL [3]VDDBL [1]Pull-up devicesBL [2] BL [3]GNDMOS NOR ROMEE141 10Programming using theActive Layer OnlyPolysiliconMetal1DiffusionMetal1 on DiffusionCell (9.5λ x 7λ)MOS NOR ROM Layout6EE141 11MOS NOR ROM LayoutPolysiliconMetal1DiffusionMetal1 on DiffusionCell (11λ x 7λ)Programming usingthe Contact Layer OnlyEE141 12All word lines high by default with exception of selected rowWL[0]WL[1]WL[2]WL[3]VDDPull-up devicesBL[3]BL[2]BL[1]BL [0]MOS NAND ROM7EE141 13No contact to VDD or GND necessary;Loss in performance compared to NOR ROMdrastically reduced cell sizePolysiliconDiffusionMetal1 on DiffusionCell (8λ x 7λ)Programming usingthe Metal-1 Layer OnlyMOS NAND ROM LayoutEE141 14Cell (5λ x 6λ)PolysiliconThreshold-alteringimplantMetal1 on DiffusionProgramming usingImplants OnlyNAND ROM Layout8EE141 15PMOS precharge device can be made as large as necessary,but clock driver becomes harder to design.WL [0]GNDBL [0]WL [1]WL [2]WL [3]VDDBL [1]Precharge devicesBL [2] BL [3]GNDprefPrecharged MOS NOR ROMEE141 16Read-Write MemoryNon-VolatileRead-WriteMemoryRead-Only MemoryEPROME2PROMFLASHRandomAccessNon-RandomAccessSRAM DRAMMask-ProgrammedProgrammable (PROM)FIFOShift RegisterCAMLIFOSemiconductor Memory Classification9EE141 17Non-Volatile MemoriesThe Floating-gate transistor (FAMOS)Floating gateSourceSubstrateGateDrainn+n+_ptoxtoxDevice cross-sectionSchematic symbolGSDEE141 180 V-5 V0 VDSRemoving programming voltage leaves charge trapped5 V-2.5 V5 VDSProgramming results inhigher VT.20 V10 V 5 V20 VDSAvalanche injectionFloating-Gate Transistor Programming10EE141 19FLOTOX EEPROMFloating gateSourceSubstratepGateDrainn1n1FLOTOX transistorFowler-NordheimI-V characteristic20–30 nm10 nm-10 V10 VIVGDEE141 20EEPROM CellWLBLVDDAbsolute threshold controlis hardUnprogrammed transistor might be depletionÖ 2 transistor cell11EE141 21EPROMFlashCourtesy IntelCross Sections of NVM CellsEE141 22Read-Write Memories (RAM) Static (SRAM)• Data stored as long as supply is applied• Large (6 transistors/cell)• Fast• Differential Dynamic (DRAM)• Periodic refresh required• Small (1-3 transistors/cell)• Slower• Single ended12EE141 23WLBLVDDM5M6M4M1M2M3BLQQ6-Transistor CMOS SRAM CellEE141 24WLBLVDDM5M6M4M1VDDVDDVDDBLQ=1Q=0CbitCbitCMOS SRAM Analysis (Read)13EE141 25CMOS SRAM Analysis (Read)000.20.40.60.811.20.5Voltage rise [V]11.2 1.5 2Cell Ratio (CR)2.5 3Voltage Rise (V)EE141 26BL=1 BL=0Q=0Q=1M1M4M5M6VDDVDDWLCMOS SRAM Analysis (Write)14EE141 27CMOS SRAM Analysis (Write)EE141 28VDDGNDQQWLBLBLM1M3M4M2M5 M6WLBLVDDM5M6M4M1M2M3BLQQ6T-SRAM Layout15EE141 29Static power dissipation -- Want RLlargeBit lines precharged to VDDto address tpproblemM3RLRLVDDWLQQM1M2M4BL BLResistive Load SRAM CellEE141 30No constraints on device ratiosReads are non-destructiveValue stored at node X when writing a “1” = VWWL-VTnWWLBL 1M1XM3M2CSBL 2RWLVDDVDD-VTDVVDD-VTBL 2BL 1XRWLWWL3-Transistor DRAM Cell16EE141 31BL2 BL1 GNDRWLWWLM3M2M1WWLBL 1M1XM3M2CSBL 2RWL3T DRAM LayoutEE141 32Write: CSis charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitanceVoltage swing is small; typically around 250 mV.M1CSWLBLCBLVDD2 VTWLXsensingBLGNDWrite 1 Read 1VDDVDD/2 VDD/2∆VBLVPRE–VBITVPRE–CSCSCBL+------------==V1-Transistor DRAM Cell17EE141 33Uses Polysilicon-Diffusion CapacitanceExpensive in AreaM1wordlineDiffusedbit linePolysilicongatePolysiliconplateCapacitorCross-sectionLayoutMetal word linePolySiO2Field Oxiden+n+Inversion layerinduced byplate biasPoly1T DRAM CellEE141 34Micrograph of 1T DRAM18EE141 35Cell Plate SiCapacitor InsulatorStorage Node Poly2nd Field OxideRefilling PolySi SubstrateTrench CellStacked-capacitor CellCapacitor dielectric layerCell plateWord lineInsulating LayerIsolationTransfer gateStorage electrodeAdvanced 1T DRAM CellsPerspectives19EE141 37EE141 Summary Digital circuit designers will have jobs in 2010+ Major challenges• Cost• Power consumption• Robustness• Complexity Some new circuit solutions and design methodologies are comingEE141 38Medium High Very HighVariabilityEnergy scaling will slow down>0.5>0.5>0.35Energy/Logic Op scaling0.5 to 1 layer per generation8-97-86-7Metal Layers11111111RC DelayReduce slowly towards 2-2.5<3~3ILD (K)Low Probability High ProbabilityAlternate, 3G etc32112016High Probability Low ProbabilityBulk Planar CMOSDelay scaling will slow down>0.7~0.70.7Delay = CV/I scaling641684210.5Integration Capacity (BT)8162232456590Technology Node (nm)2018201420122010200820062004Internal UniversityFCRP(MARCO)Courtesy: R. Krishnamurthy
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