1EE141 – Fall 2005Lecture 24Clock Distribution,Clock Distribution,InterconnectInterconnectEE141 2Administrative Stuff Homework 9 due today 5pm Project presentations next Tuesday• 9:00-12:00 (476 Cory), 2:00-5:00 (400 Cory)• Sign-up for time-slot (sign-up sheet in 353 Cory)• Presentation template on web-site2EE141 3Class Material Today’s lecture• Timing in presence of clock non-idealities• Clock distribution• Interconnect optimizationEE141 4Positive skew improves performanceNegative skew improves race marginWorst-case |δ| really mattersTClk> tc-q+ tlogic+ tsu-δthold+ δ< tc-q,cd+ tlogic,cdImpact of Clock Skew on Timing3EE141 5Outline Timing parameters Clock nonidealities (skew and jitter) Impact of Clk skew on timing Impact of Clk jitter on timing Flip-flop- vs. Latch-based timing Clock distributionEE141 6Impact of Clock JitterCLK-tji tte rTCLKtjitterCLK InCombinationalLogi c tc-q , tc-q, cdtlogictlogic, cdtsu, thol dREGStjitter1234564EE141 7ClkTClktsutc-qtlogicLatest point of launchingEarliest arrivalof next cycletjittertc-q+ tlogic+ tsu< TClk–tjitter–tjitterTClk> tc-q+ tlogic+ tsu+ 2 tjitterImpact of Clock Jitter on Timing: Cycle Time (Late-Early Problem)EE141 8TClk> tc-q+ tlogic+ tsu+ 2 tjitterNegative impact on cycle timeNo direct effect on race immunity (same Clk edge)Jitter reduces performanceImpact of Clock Jitter on Timing5EE141 9Combined Impact of Clock Jitter and Clock SkewEE141 10ClkTClktsutc-qtlogicLatest point of launchingEarliest arrivalof next cycletjitter + δtc-q+ tlogic+ tsu< TClk–tjitter–tjitter+ δTClk> tc-q+ tlogic+ tsu-δ+ 2 tjitterImpact of Clock Skew and Jitter: Cycle Time (Late-Early Problem)6EE141 11Clktc-q,cdtlogic,cdEarliest point of launchingData must not arrivebefore this timeClktholdNominalclock edgetc-q,cd+ tlogic,cd–tjitter> thold+ tjitter+ δthold+ 2 tjitter+ δ< tc-q,cd+ tlogic,cdLatest arrivalof next cycletjitter + δImpact of Clock Skew and Jitter: Race Margin (Early-Late Problem)EE141 12TClk> tc-q+ tlogic+ tsu-δ+ 2 tjitterthold+ 2 tjitter+ δ< tc-q,cd+ tlogic,cd Cycle time• Positive skew improves performance• Negative skew reduces performance• Jitter reduces performance Race Margin• Skew reduces race margin• Jitter reduces acceptable skewCombined Impact of Clock Skew and Jitter on Timing7EE141 13Outline Timing parameters Clock nonidealities (skew and jitter) Impact of Clk skew on timing Impact of Clk jitter on timing Flip-flop- vs. Latch-based timing Clock distributionEE141 14Flip-Flop – Based TimingFlip-flopLogicφφ = 1φ = 0Flip-flopdelaySkewLogic delayTSUTClk-Q[Horowitz96]8EE141 15Flip-Flops and Dynamic Logicφ = 1φ = 0Logic delayTSUTClk-Qφ = 1φ = 0Logic delayTSUTClk-QPrechargeEvaluateEvaluatePrechargeFlip-flops are used only with static logicEE141 16Latch TimingDClkQtD-QtClk-QWhen data arrives to transparent latchWhen data arrives to closed latchData has to be ‘re-launched’Latch is a ‘soft’ barrier9EE141 17Latch Timing (Cont.)DClkQDQClkTClk-QTHPWmTSUTD-QEE141 18Latch-Based DesignL1LatchLogicLogicL2LatchφL1 latch is transparentwhen Φ = 1L2 latch is transparent when Φ = 010EE141 19Latch-Based TimingL1LatchLogicLogicL2Latchφφ = 1φ = 0L1 latchL2 latchSkewCan tolerate skew!LongpathShortpathStatic logicEE141 20Outline Timing parameters Clock nonidealities (skew and jitter) Impact of Clk skew on timing Impact of Clk jitter on timing Flip-flop- vs. Latch-based timing Clock distribution11EE141 21CLKClock is distributed in a tree-like fashionH-treeClock DistributionEE141 22CLOCKH-Tree NetworkObserve: Only Relative Skew is ImportantClock Distribution12EE141 23More Realistic H-Tree[Restle98]EE141 24ModuleModuleModuleModuleModuleModuleCLOCKmain clock driversecondary clock driversReduces absolute delay, and makes Power-Down easierSensitive to variations in Buffer DelayLocal AreaClock Network with Distributed Buffering13EE141 25The Grid SystemDriverDriverDr i v e rDr i v e rGCLKGCLKGCL KGCL K•No RC-matching• Large powerEE141 26Example: Dec Alpha 21164 Clock Frequency: 300 MHz, 9.3 Million Transistors Total Clock Load: 3.75 nF Power in Clock Distribution Network: 20 W (out of 50 W) Uses Two Level Clock Distribution:• Single 6-stage driver at center of chip• Secondary buffers drive left and right side• Clock grid in Metal-3 and Metal-4• Total driver size: 58 cm!14EE141 27 Single-phase clocking 2 distributed driver channels•Reduced RC delay/skew• Improved thermal distribution• 3.75 nF clock load• 58 cm final driver width Local inverters for latching Conditional clocks in caches to reduce power More complex race checking Device variationtrise= 0.35nstskew= 150pstcycle= 3.3nsClock waveformLocation of clockdriver on diepre-driverfinal drivers21164 Clocking (EV5), 1995EE141 28Clock Drivers15EE141 29Clock Skew in Alpha ProcessorEE141 30 Multiple conditional buffered clocks•2.8 nF clock load• 40 cm final driver width Reduced load/skew Reduced thermal issues Multiple clocks complicate race checkingtrise= 0.15ns tskew= 50pstcycle= 1.67nsGlobal clock waveformPLLEV6 (Alpha 21264) Clocking 600 MHz, 0.35µm CMOS, 199816EE141 3121264 ClockingEE141 32GCLK Skew(at Vdd/2 Crossings)ps5101520253035404550ps300305310315320325330335340345GCLK Rise Times(20% to 80% Extrapolated to 0% to 100%)EV6 Clock Results17EE141 33GCLK(CPU Core)L2L_CLK(L2 Cache)L2R_CLK(L2 Cache)NCLK(Mem Ctrl)DLLPLLSYSCLKDLLDLL+ widely dispersed drivers+ DLLs compensate static and low-frequency variation+ divides design and verification effort- DLL design and verification is added work+ tailored clocksActive Skew Management and Multiple Clock DomainsEV7 Clock Hierarchy, 2002152 million transistors, 15/137 logic/memoryEE141 34Alpha Processors Case Study EV4 (21064) 0.75µm, 200 MHz ~ 1992• Single global clock driver, 5 levels of buffering− 35 cm driver, 3.25 nF, 40% power EV5 (21164) 0.5µm, 300 MHz ~ 1995• One central, two side clock drivers− 58 cm driver, 3.75 nF, 40% power EV6 (21264) 0.35µm, 600 MHz ~ 1998• Clock grid, 4 window panes, hierarchical, gated clock domains− 40 cm driver, 2.8 nF EV7 0.18µm, 1.2 GHz ~ 2002• Multiple clock domains, DLLs18EE141 35Functions of clock in synchronous design1) Acts as completion signal2) Ensures the correct ordering of eventsTruly asynchronous design2) Ordering of events is implicit in logic1) Completion is ensured by careful timing
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