1EE141 – Fall 2005Lecture 9CMOS ScalingCMOS ScalingEE141 2Admin Page This week• Lab 4 this week• Homework #4 due Thursday 9/29, 5pm Next week• No new homework due next week• No labs next week• Midterm 1 is next Thursday, Oct 6, 6:30-8pm (TBD) Hw-2 stats• 94% had > 80% (32/40)• 85% had > 90% (36/40)2EE141 3Midterm #1 Thursday, October 6, 6:30-8:00pm, (TBD) Material up to (including) Lecture-9 (Scaling)• Ch-1, Ch-2, Ch-3, Ch-5 Open book, open notes Past Midterms on the web Review: Tuesday, Oct 4, 6:30-8:30pm (TBD)EE141 4Interesting Presentations… Wednesday, Sep-28, 4pm, 306 Soda Hall“Multi-Core Systems”by Michael RosenfieldDirector, VLSI Systems, IBM Research IC Seminar, Mondays, 4pm, 521 Cory3EE141 5Last Lecture Last lecture• Buffer sizing• Power dissipation Today’s lecture• CMOS scalingImpact of Impact of Technology ScalingTechnology Scaling4EE141 7Goals of Technology Scaling Make things cheaper:• Want to sell more functions (transistors) per chip for the same money• Build same products cheaper, sell the same part for less money• Price of a transistor has to be reduced But also want to be faster, smaller, lower powerEE141 8Technology Scaling Technology generation spans 2-3 years Benefits of scaling the dimensions by 30%:• Reduce gate delay by 30% (increase operating frequency by 43%)• Double transistor density• Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency) Die size used to increase by 14% per generation5EE141 9Technology GenerationsEE141 10International Technology Roadmap for SemiconductorsNode years: 2007/65nm, 2010/45nm, 2013/32nm, 2016/22nmYear 2001 2003 2005 2007 2010 2013 2016 DRAM ½ pitch [nm] 130 100 80 65 45 32 22 MPU transistors/chip 97M 153M 243M 386M 773M 1.55G 3.09G Wiring levels 8 8 10 10 10 11 11 High-perf. phys. gate [nm] 65 45 32 25 18 13 9 High-perf. VDD [V] 1.2 1.0 0.9 0.7 0.6 0.5 0.4 Local clock [GHz] 1.7 3.1 5.2 6.7 11.5 19.3 28.8 High-perf. power [W] 130 150 170 190 218 251 288 Low-power phys. gate [nm] 90 65 45 32 22 16 11 Low-power VDD [V] 1.2 1.1 1.0 0.9 0.8 0.7 0.6 Low-power power [W] 2.4 2.8 3.2 3.5 3.0 3.0 3.0 Technology Roadmap (2002)6EE141 11ITRS Technology Roadmap Acceleration ContinuesEE141 12Minimum Feature Size1960 1970 1980 1990 2000 201010-210-1100101102YearMinimum Feature Size (micron)Technology Scaling (1)Today 90nm~2x reduction / 5 years7EE141 13Number of components per chip Technology Scaling (2)EE141 14Propagation Delaytpdecreases by 30%/yearf increases by 43%Technology Scaling (3)8EE141 15Technology Scaling (4)(a) Power dissipation vs. year.959085800.010.1110100YearPower Dissipation (W)x4 / 3 yearsMPU DSPx1.4 / 3 yearsScaling Factor κ （normalized by 4µm design rule）1011101001000∝ κ 3Power Density (mW/mm2)∝ κ 0.7(b) Power density vs. scaling factor.From KurodaISSCC dataEE141 16Technology Scaling Models Full Scaling (Constant Electric Field)• Ideal model• Dimensions and voltages scale by the same factor S Fixed Voltage Scaling• Most common model until recently• Only dimensions scale, voltages remain constant General Scaling• Most realistic for today situation• Voltages and dimensions scale with different factors9EE141 17Scaling (Long Channel Devices)EE141 18S2S2/U21Power/AreaP Density11/U21/S2IsatVPower1/S1/S1/SRonCgateIntr. Delay111V / IsatRonS2S2/USIsat/ AreaCrnt Density11/U1/SCoxWVIsatSSSCoxW/Lkn, kp1/S1/S1/SCoxWLCgateSSS1/toxCox1/S21/S21/S2WLArea/Device11/U1/SVDD, VT1/S1/S1/SW, L, toxFixed V Sc.General Sc.Full ScalingRelationParameterScaling (Short Channel Devices)10EE141 19µProcessor Scaling40048008808080858086286386486Pentium® procP60.0010.010.111010010001970 1980 1990 2000 2010YearTransistors (MT)2X growth in 1.96 years!S. Borkar, IEEE Micro 1999,P. Gelsinger, µProcessors for the New Millennium, ISSCC 2001.EE141 20µProcessor Power5KW 18KW 1.5KW 500W 40048008808080858086286386486Pentium® proc0.11101001000100001000001971 1974 1978 1985 1992 2000 2004 2008YearPower (Watts)S. Borkar, IEEE Micro 1999,P. Gelsinger, µProcessors for the New Millennium, ISSCC 2001.11EE141 21µProcessor PerformanceP. Gelsinger, µProcessors for the New Millennium, ISSCC 2001EE141 222010 Outlook Performance• 1 TIP (terra instructions/s)• 30 GHz clock Size• No of transistors: 2 Billion• Die: 40*40 mm Power• 10kW!!• Leakage: 1/3 of total PowerP. Gelsinger, µProcessors for the New Millennium, ISSCC 200112EE141 23Some Interesting Questions What will cause this model to break? When will it break? Will the model gradually slow down?• Power and power density• Leakage• Process VariationWiresWires13EE141 25The Wireschematics physicaltransmittersreceiversEE141 26Interconnect Impact on Chip14EE141 27Wire ModelsAll-inclusive modelCapacitance-onlyEE141 28 Interconnect parasitics• reduce reliability• affect performance and power consumption Classes of parasitics• Capacitive• Resistive• InductiveImpact of Interconnect Parasitics15EE141 29Nature of InterconnectLocal InterconnectGlobal InterconnectSLocal = STechnologySGlobal= SDie10 100 1,000 10,000 100,000Length (µm)Pentium Pro (R)Pentium (R) IIPentium (MMX)Pentium (R)Pentium (R) IIINo of nets(log scale)Source: IntelInterconnectInterconnectCapacitanceCapacitance16EE141 31VDDVDDVinVoutM1M2M3M4Cdb2Cdb1Cgd12CwCg4Cg3Vout2FanoutInterconnectVoutVinCLSimplifiedModelCapacitance of Wire InterconnectEE141 32WLtcdidiintε=LLCwireSSSSS1=⋅=Capacitance: The Parallel Plate ModelDielectricLWHElectrical-field linesCurrent flowtdiSubstrate17EE141 33PermittivityEE141 34W - H/2H+(a)(b)Fringing Capacitancefringepp18EE141 35Fringing vs. Parallel PlateFrom: Bakoglu89EE141 36Interwire Capacitancefringingparallel19EE141 37Impact of Interwire CapacitanceFrom: Bakoglu89EE141 38Wiring Capacitances (0.25µm)20EE141 39Next Lecture Wires• Resistance• Capacitance•
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