EE1411EECS1411Lecture #15EE141EE141--Fall 2009Fall 2009Digital Integrated Digital Integrated CircuitsCircuitsLecture 15Lecture 15SRAM Circuit DesignSRAM Circuit DesignEE1412EECS1412Lecture #15AnnouncementsAnnouncements Homework #6 due today Homework #7 due next Thurs. Project #1 out next Thurs. Software labs complete Turn in reports for lab #5 next week during first 30 mins of lab timeEE1413EECS1413Lecture #15SRAM Circuit SRAM Circuit DesignDesignEE1414EECS1414Lecture #1566--transistor CMOS SRAM Cell transistor CMOS SRAM Cell WLBLVDDM5M6M4M1M2M3BLQQEE1415EECS1415Lecture #15SRAM ColumnSRAM ColumnWL2WL0WL3BLBL_BEE1416EECS1416Lecture #15SRAM OperationSRAM Operation0101WriteHoldEE1417EECS1417Lecture #15SRAM OperationSRAM Operation01• Q_b will get pulled up when WL first goes high• Reading the cell should not destroy the stored valueReadEE1418EECS1418Lecture #15CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)51DD=IIWLBLVDDM5M6M4M1VDDVDDVDDBLQ=1Q=0CbitCbit∆V()215,5 12DD Tnsat ox n ox DD TnDD Tn crit nVV VWVWv C C V V VVV V L Lµξ−−∆∆⎛⎞=−−∆⎜⎟−−∆+⎝⎠EE1419EECS1419Lecture #15CMOS SRAM Analysis (Read)CMOS SRAM Analysis (Read)000.20.40.60.811.20.5Voltage rise [V]11.2 1.5 2Cell Ratio (CR)2.5 3Voltage Rise (∆V)EE14110EECS14110Lecture #15CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write) BL=1 BL=0Q=0Q=1M1M4M5M6VDDVDDWL()264,4 62DD TpQsat ox n ox DD Tn QDD Tp crit pVVVWWv C C V V VVV L Lµξ−⎛⎞=−−⎜⎟−+⎝⎠EE14111EECS14111Lecture #15CMOS SRAM Analysis (Write)CMOS SRAM Analysis (Write)()()64//LWLWPR =EE14112EECS14112Lecture #15Read Static Noise MarginRead Static Noise MarginSNMObtained by breaking thefeedback between the invertersEE14113EECS14113Lecture #15Write Static Noise MarginWrite Static Noise MarginEE14114EECS14114Lecture #15Alternate Definition for Write MarginAlternate Definition for Write MarginEE14115EECS14115Lecture #15Next LectureNext Lecture Power
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