L10: 6.111 Spring 20041Introductory Digital Systems LaboratoryL10: Major/Minor L10: Major/Minor FSMsFSMs, , Lab 3, and RAM/ROM InstantiationLab 3, and RAM/ROM InstantiationAcknowledgements: Rex MinL10: 6.111 Spring 20042Introductory Digital Systems LaboratoryToward FSM ModularityToward FSM Modularity Consider the following abstract FSM:S0a1b1c1d1S1S2S3S4S5S6S7S8S9a2b2c2d2a3b3c3d3 Suppose that each set of states ax...dxis a “sub-FSM” that produces exactly the same outputs. Can we simplify the FSM by removing equivalent states?No! The outputs may be the same, but the next-state transitions are not. This situation closely resembles a procedure call or function callin software...how can we apply this concept to FSMs?L10: 6.111 Spring 20043Introductory Digital Systems LaboratoryThe Major/Minor FSM AbstractionThe Major/Minor FSM Abstraction Subtasks are encapsulated in minor FSMs with common reset and clock Simple communication abstraction: START: tells the minor FSM to begin operation (the call) BUSY: tells the major FSM whether the minor is done (the return) The major/minor abstraction is great for... Modular designs (always a good thing) Tasks that occur often but in different contexts Tasks that require a variable/unknown period of time Event-driven systemsMajor FSMMinor FSM AMinor FSM BSTARTASTARTBBUSYABUSYBCLKRESETRESETCLKL10: 6.111 Spring 20044Introductory Digital Systems LaboratoryInside the Major FSMInside the Major FSMS1S2STARTS3S4...BUSYBUSYBUSYBUSYBUSY BUSY1. Wait until the minor FSM is ready2. Trigger the minor FSM (and make sure it’s started)3. Wait until the minor FSM is doneSTARTBUSYMajor FSM StateS1S2S2S3S3S3S4CLKL10: 6.111 Spring 20045Introductory Digital Systems LaboratoryInside the Minor FSMInside the Minor FSMT2BUSYT3BUSYT4BUSY1. Wait for a trigger from the major FSM2. Do some useful workT1BUSYSTARTSTARTSTARTBUSYMajor FSM StateS1S2S2S3S3S3S4CLKMinor FSM StateT1T1T2T3T4T1T13. Signal to the major FSM that work is donecan we speed this up?L10: 6.111 Spring 20046Introductory Digital Systems LaboratoryOptimizing the Minor FSMOptimizing the Minor FSMT2BUSYT3BUSYT4BUSYT1BUSYSTARTSTARTGood idea: de-assert BUSY one cycle earlyBad idea #1:T4may not immediately return to T1T2BUSYT3BUSYT1BUSYSTARTSTARTT4BUSYBad idea #2:BUSY never asserts!T1BUSYSTARTSTARTT2BUSYL10: 6.111 Spring 20047Introductory Digital Systems LaboratoryA FourA Four--FSM ExampleFSM ExampleOperating Scenario: Major FSM is triggered by TICK Minors A and B are started simultaneously Minor C is started once both A and B complete TICKs arriving before the completion of C are ignoredMajor FSMMinor FSM AMinor FSM BSTARTASTARTBBUSYABUSYBMinor FSM CSTARTCBUSYCTICKIDLESTABSTARTASTARTBWTABTICKBUSYABUSYBTICKBUSYA+BUSYBBUSYA+BUSYBSTCSTARTCBUSYABUSYBBUSYCWTCBUSYCBUSYCBUSYCAssume that BUSYAand BUSYBboth rise before either minor FSM completes. Otherwise, we loop forever!L10: 6.111 Spring 20048Introductory Digital Systems LaboratoryFourFour--FSM Sample WaveformFSM Sample WaveformIDLE IDLESTABSTABWTABWTABWTABSTCSTCWTCWTCWTCIDLE IDLE STABstatetickSTARTABUSYASTARTBBUSYBSTARTCBUSYCMajor FSMMinor FSM AMinor FSM BSTARTASTARTBBUSYABUSYBMinor FSM CSTARTCBUSYCTICKL10: 6.111 Spring 20049Introductory Digital Systems LaboratoryLab3 Block DiagramLab3 Block DiagramD/AAD 558A/DAD 670statuscontrol(CE, CS, R/W)MAJOR FSMMINORFSM 1MINORFSM 2...SynchronizerBidirectionalI/O8SRAMArithmetic UnitCONTROL UNITD/A RegA/D RegLE_ADCBypassLE_DACLE_DAC8 ROM88ALUCONTROLRAMCont rol88cont rol(CE, CS)SW2SwitchesSWRESETCLKImpulse Response ROM(MAC)LDDQLDDQand Ad d res s Contro l and Address8 Must choose a shared bus for the A/D and DA A/D output in twos complement and ROM in sign/magnitude Use on-chip SRAM and ROMSample rate is fixedat 20kHzMust use a memorybased approach to FIR, not tapped delayline (i.e., registers) Must use Major/MinorFSM structureL10: 6.111 Spring 200410Introductory Digital Systems LaboratoryControl Flow for Lab3Control Flow for Lab3InitializeWaitOutput ComputedSample to DACResetStore A/DSampleInitiate A/DConvolveSampleSample Wait for a fixed time interval. Output what was computed on the last sample. Store the previous A/D sample into memory. Start the next A/D conversion. Do the FIR filter algorithm which is a convolution. Go back for more...L10: 6.111 Spring 200411Introductory Digital Systems LaboratoryUse LPM to Create ROM/RAMUse LPM to Create ROM/RAM Click on File → MegaWizard Plug-In ManagerThis starts up a series of windows so that you can specify parameters of the LPM module. You can choosez ROMz RAM dp - Dual Ported dq - Separate Inputs and Outputs io - TriState Inputs and Outputs (like the 6264)You choose the number of address bits and the word size.You should specify a file to set the values of the ROM.You can choose registered or unregistered inputs, outputs, and addresses.L10: 6.111 Spring 200412Introductory Digital Systems LaboratoryROM ContentsROM Contents Prepare a .dat file. You can type this in, write a computer program, get it from another application (speech or graphics, etc.) This has numbers separated by white space.z The default base is HEX but you can use binary or decimal if you include the following statement (before the numbers).# BASE = BINARY; Insert, # SET_ADDRESS = 0; (specifies that data should start at address 0) Run dat2ntl on Athena to format your .dat file into Intel HEX for details, after ‘setup 6.111’ type ‘man dat2ntl’ dat2ntl <filename>.dat <filename>.ntlrom8x8.ntl::080000000706050403020100DC:00000001FFrom8x8.dat:# SET_ADDRESS = 0;76543210dat2ntltool on athena3ROM8addressdataSee http://web.mit.edu/6.111/www/s2004/software.html for .mif format (memory initialization format)L10: 6.111 Spring 200413Introductory Digital Systems Laboratoryrom8x8.v (generated automatically)rom8x8.v (generated automatically)//=============================================// File Name: rom8x8.v// Megafunction Name(s):// lpm_rom//=============================================module rom8x8 (address,q);input [2:0] address;output [7:0] q;wire [7:0] sub_wire0;wire [7:0] q = sub_wire0[7:0];lpm_rom lpm_rom_component (.address (address),.q (sub_wire0));defparamlpm_rom_component.lpm_width = 8,lpm_rom_component.lpm_widthad = 3,lpm_rom_component.lpm_address_control = "UNREGISTERED",lpm_rom_component.lpm_outdata = "UNREGISTERED",lpm_rom_component.lpm_file =
View Full Document
Unlocking...