Michael Huhs 6.111 Final Project Code //Write Module module write_module(clk, reset, master_in, data_enable, sram_addr, we, sram_data_out, dct_data_out, RST, rdy_out, dct_data_in, cen, dimension, blocks, start_address); input clk, reset; //Control interface input [7:0] master_in; input data_enable; output reg [35:0] sram_data_out; output reg [18:0] sram_addr; output reg we; output reg cen; //DCT interface output reg [7:0] dct_data_out; output reg RST; input rdy_out; input [11:0] dct_data_in; input [3:0] dimension; input [13:0] blocks; input [18:0] start_address; reg [3:0] column_count; reg [3:0] row_count; reg [13:0] block_count; //reg [3:0] size; reg [2:0] state; parameter idle = 0; parameter wait_for_dct = 1; parameter write_to_sram = 2; parameter skip_write = 3; always @ (posedge clk) begin if (data_enable) dct_data_out <= master_in; else dct_data_out <= 0; end always @ (posedge clk) case (state)idle: begin if (data_enable) begin state <= wait_for_dct; //dct_data_out <= master_in; RST <= 0; cen <= 0; end else begin sram_addr <= 0; sram_data_out <= 0; state <= idle; we <= 0; RST <= 1; column_count <= 0; row_count <= 0; block_count <= 0; //size <= dimension; cen <= 0; //dct_data_out <= 0; end end wait_for_dct: begin if (reset) state <= idle; else begin if(!rdy_out) begin state <= wait_for_dct; sram_addr <= start_address; //if (data_enable) dct_data_out <= master_in; end else begin state <= write_to_sram; //if (data_enable) dct_data_out <= master_in; we <= 1; cen <= 1; sram_data_out <= {24'b0,dct_data_in}; column_count <= 1; row_count <= 1; block_count <= 1; end end endwrite_to_sram: begin if (reset) begin state <= idle; RST <= 1; end else begin if(column_count < dimension) begin //if (data_enable) dct_data_out <= master_in; sram_data_out <= {24'b0,dct_data_in}; sram_addr <= sram_addr + 1; column_count <= column_count + 1; we <= 1; cen <= 1; state <= write_to_sram; end else begin if (dimension == 8)begin sram_data_out <= {24'b0,dct_data_in}; sram_addr <= sram_addr + 1; column_count <= column_count + 1; we <= 1; cen <= 1; state <= write_to_sram; end else begin state <= skip_write; we <= 0; cen <= 1; //if (data_enable) dct_data_out <= master_in; column_count <= column_count + 1; sram_addr <= sram_addr + 1; sram_data_out <= 0; //if ((row_count >= (size - 1)) && ((size - 1) > 0)) size <= (size - 1); end end end end skip_write: begin if (reset) state <= idle; else beginif(column_count < 8) begin column_count <= column_count + 1; state <= skip_write; cen <= 1; //if (data_enable) dct_data_out <= master_in; end else begin if (row_count == 8) begin if (block_count >= blocks) begin state <= idle; we <= 0; sram_addr <= 0; sram_data_out <= 0; RST <= 1; column_count <= 0; row_count <= 0; block_count <= 0; cen <= 0; end else begin row_count <= 1; column_count <= 1; block_count <= block_count + 1; sram_data_out <= {24'b0,dct_data_in}; we <= 1; cen <= 1; state <= write_to_sram; end end else begin if (row_count >= dimension) begin column_count <= 1; row_count <= row_count + 1; we <= 0; cen <= 1; state <= skip_write;end else begin column_count <= 1; row_count <= row_count + 1; we <= 1; cen <= 1; sram_data_out <= {24'b0, dct_data_in}; state <= write_to_sram; end end end end end default: begin state <= idle; we <= 0; sram_addr <= 0; sram_data_out <= 0; RST <= 1; column_count <= 0; row_count <= 0; block_count <= 0; cen <= 0; //dct_data_out <= 0; end endcase endmodule//Read Module module read_module(clk, reset, read_frame, compression, blocks, start_address, ram_address, sram_read_data, idct_data_out, idct_data_in, rdy, RST, master_out, data_ready, done); //image size is 480 x 712 //(480 x 712 / 8) = 5340 blocks // 5340 * 64 = 341,760 pixels + 93 for latency = done goes high 341,853 clock cycles from rdy high input clk, reset, read_frame; input [18:0] start_address; input [3:0] compression; input [35:0] sram_read_data; input [7:0] idct_data_in; input [13:0] blocks; output reg rdy, RST, done; output reg [18:0] ram_address; output reg [11:0] idct_data_out; output reg [7:0] master_out; output reg data_ready; reg [3:0] read_column_count; reg [3:0] read_row_count; reg [13:0] read_block_count; reg [2:0] state; reg [18:0] count; reg [3:0] wait_count; parameter idle = 0; parameter wait_for_sram =1; parameter pass_to_idct = 2; parameter pass_zeros = 3; parameter idct_output = 4; always @ (posedge clk) begin if (count > 93) begin master_out <= idct_data_in; data_ready <= 1; end else begin master_out <= 0; data_ready <= 0; end endalways @ (posedge clk) case (state) idle: begin if (read_frame) begin state <= wait_for_sram; ram_address <= start_address; wait_count <= 2; RST <= 0; end else begin state <= idle; rdy <=0; RST <= 1; wait_count <= 0; ram_address <= 0; idct_data_out <= 0; read_column_count <=0; read_row_count <=0; read_block_count <=0; count <= 0; done <= 0; end end wait_for_sram: begin if (reset) state <= idle; else begin if (wait_count > 0)begin ram_address <= ram_address + 1; wait_count <= wait_count - 1; end else begin state <= pass_to_idct; rdy <= 1; count <= count + 1; idct_data_out <= sram_read_data[11:0]; read_column_count <= 1; read_row_count <= 1; ram_address <= ram_address + 1; end end endpass_to_idct: begin if (reset) state <= idle; else begin if (read_column_count == (compression - 1))begin if (compression == 7) ram_address <=
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