Specifications and RequirementsAnalog to Digital ConversionDigital to Analog ConversionWireless Headphones6.111 Final ProjectNivedita ChandrasekaranJessica NesvoldAditi ShrikumarOverviewAnalog to Digital……Digital to Analog0101010111010001010101010101110101010100 Aditi S. 0101101010101010101001111110101010101010Specifications and Requirements• No aliasing: at least 44-kHz sampling rate• High resolution: at least 8 bit bits per sample• Stereo: two samples per sampling period• Wireless transmission rates: not too many bits per sampleAnalog to Digital ConversionDigital to Analog ConversionMONPRESSIOCDECOMPRESSIONJessica N.80 bits15 015 015 015 015 0N1N2N3N4N5015161920212425262930313435363940 bitsN1first1sdiff2sdiff3diff4diff5 ssCodec – Big Picture• Lossy vs. Losslessstate_shiftrN1_in <=N1_in >> (15 – first1)state <= state_set1state_shiftlN1_in <=N1_in << (15 – first1)state <= state_N2state_set1N1_in[15] <= 1state <= state_shiftrstate_donevalid_out <= 1state_N3if (N3_sign == 0)N3 <= N2 + N3_diffelseN3 <= N2 – N3_diffstate <= state_N4state_N4if (N4_sign == 0)N4 <= N3 + N4_diffelseN4 <= N3 – N4_diffstate <= state_N4state_N5if (N5_sign == 0)N5 <= N4 + N5_diffelseN5 <= N4 – N5_diffstate <= state_donestate_N2if (N2_sign == 0)N2 <= N1 + N2_diffelseN2 <= N1 – N2_diffstate <= state_N3DecompressionWirelessNivedita C.Wireless – Operation, Specifications and Requirements• Hardware: Two CC2420 transceivers mounted on two evaluation boards• All communication with chips implemented in Verilog• Talk to chips via a Serial Peripheral (SPI) interface clocked at 10MHz•All operations performed by writing or reading from 33 16-bit configuration registers and 15 8-bit command strobe registers CC2420>CSnSISCLKSOGeneral Transceiver Block DiagramSPI MasterTransmit Mode Receive ModeConfiguration ModeFIFO Bufferbegin_configdone_configbegin_transdone_trans(125*4)trans_packetbegin_recdone_rec(125*4)rec_packetsuccesssuccess(125*4)t_packet(125*4)r_packet2f_opConfig_ROM8x2424config_datastatusnImplementation Issues• Data Throughput• Chipcon specs: max data rate ~250 kbps• Overhead: includes frame check sequences, may have to introduce error correction sequences• Assumes uninterrupted transmission• Memory buffer sizes• The lower the data rate, the greater the required size of the buffers • Dealing with two labkit clocks• Need to time interaction of two halves of the system properly• Solution: Handshake/acknowledgement protocol between transmitter and
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