Part 1: Analog InterfaceBe Able to Demonstrate Your Working LabBe Able to Respond to any of the Following Questions (and possibly others)Student Name:Part 2: Complete Digital Filter (including analog blocks)Be Able to Demonstrate Your Working LabBe Able to Respond to any of the Following Questions (and possibly others)1. Introduction2. Procedure3. System DescriptionFigure 1 : Overall block diagram.Figure 2 : Overall control flow.4. System OrganizationFigure 3 : Detailed block diagram.5. Analog Blocks and CheckoffA/D converterBidirectional Output, A/D and D/A RegistersSystem ClockConvolution OperationFigure 4 : Multiply-Accumulate Unit.Global Reset SignalStorage Unit (SRAM)Table 1: Switches8. Laboratory Report Requirements(c) Timing diagrams for major signals - refer to these timing diagrams in your detailed descriptions.Testing/Debugging1Massachusetts Institute of TechnologyDepartment of Electrical Engineering and Computer Science6.111 - Introductory Digital Systems LaboratoryLaboratory 3 Check Off SheetStudent Name:TA Signature/Date:Part 1: Analog Interface You must show a TA the following at the beginning of the analog check off• State transition diagram of your FSM(s). • Verilog code. • Timing diagrams for your D/A and A/D. Be Able to Demonstrate Your Working Lab• You will be asked to demonstrate the correct performance of your A/D and D/A by simply reconstructing the signal sampled by your A/D at the output of your D/A.Be Able to Respond to any of the Following Questions (and possibly others)• What are the critical timing constraints of your A/D and D/A system?• Explain the operation and importance of your tri-state bus.• Can you have glitches on the control inputs CS, CE, R/W for the A/D?• Can you have glitches on the control inputs CS, CE for the D/A?2Student Name:TA Signature/Date:Part 2: Complete Digital Filter (including analog blocks) You must show a TA the following at the beginning of the analog check off• Block diagram for your system.• State transition diagrams for your major-minor FSM structure.• Verilog code printout.Be Able to Demonstrate Your Working Lab• From reset, demonstrate that you can filter an input signal with any of the 4 impulse responses provided.Be Able to Respond to any of the Following Questions (and possibly others)• Describe the critical timing issues of your system.• What are the possible problem(s) with the shared tristate bus structure? • For the clock frequency you used, what is the fastest sampling rate possible?• Can you suggest ways to improve the throughput of the system?3 Massachusetts Institute of TechnologyDepartment of Electrical Engineering and Computer Science6.111 - Introductory Digital Systems LaboratoryLaboratory 3 - Finite Impulse Response FilterIssued: March 3, 2004Analog Checkoff: March 19, 2004Final Checkoff and Report Due: April 2, 20041. IntroductionYou will design a 16-tap Finite Impulse Response Filter (FIR) in this lab, suitable for filtering inputs froma signal generator or audio signals from a music player or microphone. Like the previous labs, you willneed to design finite state machines to control your subsystems. Additionally, you will need to instantiatesome modules and build controllers to interface an analog to digital converter and a digital to analog con-verter to your FPGA. 2. ProcedureThis lab consists of three parts. The first part is the design phase, which is very similar to the previous labs.You should read through the lab and plan your design. It will be helpful to schedule a design conferencewith your TA or the professor to help with your design.The second part of this lab is the Analog Checkoff. You are asked to connect the A/D converter, FPGA,and D/A together to sample an analog signal, and reconstruct this signal at the output of the D/A converter. The third part of the lab is to expand on the analog part and implement the convolution to complete the FIRfilter. You will need to instantiate your custom parallel multiplier, an accumulator, a ROM, a RAM andand additional FSMs to control and coordinate these modules. Your design structure should be such that atop-level FSM controls other minor FSMs, which in turn control different blocks in your system. You arefree to choose what modules your minor FSMs will control, for example, you might choose to control themultiplier and the accumulator by one FSM, memory units by another FSM and analog interfaces withother FSMs (for this design, it is probably just as easy to implement all the necessary logic in a singleFSM, but we would like you to go through the process of modular design using the Major/Minor FSMapproach).You will be required to turn in a detailed report for this lab.3. System DescriptionYour task is to build a machine which will accept analog signals and produce a filtered version of the inputsignal. We will choose the FIR (Finite Impulse Response) convolution approach for digital filtering, whichis widely used by filter designers. Digital Signal Processors (DSP) are well suited to perform multiplica-tion and addition operations and the FIR filter is a standard signal processing benchmark.4 An overall block diagram is shown in Figure 1. The basic idea is to sample analog signals using an Analog-to-Digital Converter (A/D) and store them in amemory element, perform the filtering operation in an arithmetic operation unit, and send the result to aDigital-to-Analog Converter (D/A). The major sequence of operations are shown in Figure 2. First, initialize the system as required, then wait until the next sample (sample is a one cycle pulse everysampling period). Output the previously computed output signal sample to the D/A converter and store theresult from the previous A/D conversion in the memory (e.g. SRAM). Initiate an A/D conversion so thatthe conversion time is overlapped (or concurrent) with the rest of the processing (why might this be impor-tant?). After that, do the arithmetic which implements the convolution filtering. Finally, loop back andwait until it is time for the next sample. Digital FilterAnalog InAnalog Out2Impulse ResponseSelection Switches ResetFigure 1: Overall block diagram.A/DD/AInitializeReset WaitSampleOutput ComputedSample to DACSampleStore A/DSampleInitiate A/DFigure 2: Overall control flow.Convolve5Note: If you are not familiar with convolution, there is problem in problem set 3 that introduces the basicsof discrete convolution. We will provide you
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