MIT 6 111 - Blocking vs. Nonblocking Assignments (24 pages)

Previewing pages 1, 2, 23, 24 of 24 page document View the full content.
View Full Document

Blocking vs. Nonblocking Assignments



Previewing pages 1, 2, 23, 24 of actual document.

View the full content.
View Full Document
View Full Document

Blocking vs. Nonblocking Assignments

118 views

Lecture Notes


Pages:
24
School:
Massachusetts Institute of Technology
Course:
6 111 - Introductory Digital Systems Laboratory
Introductory Digital Systems Laboratory Documents

Unformatted text preview:

I Blocking vs Nonblocking Assignments Verilog supports two types of assignments within always blocks with subtly different behaviors Blocking assignment evaluation and assignment are immediate always a or b or c begin x a b y a b c z b c end 1 Evaluate a b assign result to x 2 Evaluate a b c assign result to y 3 Evaluate b c assign result to z Nonblocking assignment all assignments deferred until all right hand sides have been evaluated end of simulation timestep always begin x y z end a or b or c a b a b c b c 1 Evaluate a b but defer assignment of x 2 Evaluate a b c but defer assignment of y 3 Evaluate b c but defer assignment of z 4 Assign x y and z with their new values Sometimes as above both produce the same result Sometimes not 6 111 Fall 2007 Lecture 6 Slide 1 Why two ways of assigning values Conceptual need for two kinds of assignment in always blocks a a b x b c y Blocking Evaluation and assignment are immediate a b b a x a b y x c Non Blocking Assignment is postponed until all r h s evaluations are done a b b a x a b y x c When to use Sequential Circuits only in always blocks 6 111 Fall 2007 Combinational Circuits Lecture 6 Slide 2 Assignment Styles for Sequential Logic Flip Flop Based Digital Delay Line in D Q q1 D Q q2 D Q out clk Will nonblocking and blocking assignments both produce the desired result module nonblocking in clk out input in clk output out reg q1 q2 out always posedge clk begin q1 in q2 q1 out q2 end endmodule 6 111 Fall 2007 module blocking in clk out input in clk output out reg q1 q2 out always posedge clk begin q1 in q2 q1 out q2 end endmodule Lecture 6 Slide 3 Use Nonblocking for Sequential Logic always posedge clk begin q1 in q2 q1 out q2 end always posedge clk begin q1 in q2 q1 out q2 end At each rising clock edge q1 q2 and out simultaneously receive the old values of in q1 and q2 At each rising clock edge q1 in After that q2 q1 in After that out q2 q1 in Finally out in q1 in D Q D Q in out q1 q2 D Q out clk clk D Q q2 Blocking



View Full Document

Access the best Study Guides, Lecture Notes and Practice Exams

Loading Unlocking...
Login

Join to view Blocking vs. Nonblocking Assignments and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Blocking vs. Nonblocking Assignments and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?