6.111 Fall 2007 Lecture 6, Slide 11. Evaluate a | b but defer assignment of x2. Evaluate a^b^c but defer assignment of y3. Evaluate b&(~c) but defer assignment of z1. Evaluate a | b, assign result to x 2. Evaluate a^b^c, assign result to y 3. Evaluate b&(~c), assign result to z I. Blocking vs. Nonblocking Assignments• Verilog supports two types of assignments within alwaysblocks, with subtly different behaviors.•Blocking assignment: evaluation and assignment are immediate•Nonblocking assignment: all assignments deferred until allright-hand sides have been evaluated (end of simulationtimestep)• Sometimes, as above, both produce the same result.Sometimes, not!always @ (a or b or c)begin x = a | b; y = a ^ b ^ c; z = b & ~c;endalways @ (a or b or c)begin x <= a | b; y <= a ^ b ^ c; z <= b & ~c;end4. Assign x, y, and z with their new values6.111 Fall 2007 Lecture 6, Slide 2Why two ways of assigning values?Conceptual need for two kinds of assignment (in always blocks):abcxyaba = bb = ax = a & by = x | cBlocking:Evaluation and assignmentare immediatea <= bb <= ax <= a & by <= x | cNon-Blocking:Assignment is postponed untilall r.h.s. evaluations are doneWhen to use:SequentialCircuitsCombinationalCircuits( only in always blocks! )6.111 Fall 2007 Lecture 6, Slide 3Assignment Styles for Sequential Logic• Will nonblocking and blocking assignments bothproduce the desired result?module nonblocking(in, clk, out); input in, clk; output out; reg q1, q2, out; always @ (posedge clk) begin q1 <= in; q2 <= q1; out <= q2; endendmoduleD QD QD Qin outq1 q2clkFlip-Flop BasedDigital DelayLinemodule blocking(in, clk, out); input in, clk; output out; reg q1, q2, out; always @ (posedge clk) begin q1 = in; q2 = q1; out = q2; endendmodule6.111 Fall 2007 Lecture 6, Slide 4Use Nonblocking for Sequential LogicD QD QD Qin outq1 q2clk always @ (posedge clk) begin q1 <= in; q2 <= q1; out <= q2; end“At each rising clock edge, q1, q2, andout simultaneously receive the old valuesof in, q1, and q2.” always @ (posedge clk) begin q1 = in; q2 = q1; out = q2; end“At each rising clock edge, q1 = in.After that, q2 = q1 = in; After that,out = q2 = q1 = in; Finally out = in.”• Blocking assignments do not reflect the intrinsic behavior ofmulti-stage sequential logic• Guideline: use nonblocking assignments forsequential always blocksD Qinoutclkq1 q26.111 Fall 2007 Lecture 6, Slide 5x <= a & b;0 1 0 1 1 x<=0Assignment completion0 1 0 0 1Use Blocking for Combinational Logic• Nonblocking assignments do not reflect the intrinsic behavior ofmulti-stage combinational logic• While nonblocking assignments can be hacked to simulate correctly(expand the sensitivity list), it’s not elegant• Guideline: use blocking assignments forcombinational always blocks(Given) Initial ConditionBlocking Behaviora b c x y1 1 0 1 1(Given) Initial Conditiona b c x y Deferred1 1 0 1 1Nonblocking Behavior always @ (a or b or c) begin x <= a & b; y <= x | c; end always @ (a or b or c) begin x = a & b; y = x | c; endabcxya changes;always block triggered0 1 0 1 1x = a & b;0 1 0 0 1y = x | c;0 1 0 0 0a changes;always block triggered0 1 0 1 1y <= x | c;0 1 0 1 1 x<=0, y<=16.111 Fall 2007 Lecture 6, Slide 6II. Single-clock Synchronous CircuitsSingle-clock Synchronous Discipline:• No combinational cycles• Only care about value ofcombinational circuits justbefore rising edge of clock• Period greater than every combinational delay• Change saved state after noise-inducing logic transitions havestopped!We’ll use Flip Flops and Registers – groups of FFs sharing a clock input – in ahighly constrained way to build digital systems.• Single clock signal shared amongall clocked devices6.111 Fall 2007 Lecture 6, Slide 7Clocked circuit for on/off buttonmodule onoff(clk,button,light); input clk,button; output light; reg light; always @ (posedge clk) begin if (button) light <= ~light; endendmoduleD QBUTTONLIGHTCLK01QDLECLKLOAD-ENABLED REGISTERSINGLE GLOBAL CLOCKDoes this workwith a 1MhzCLK?6.111 Fall 2007 Lecture 6, Slide 8Asynchronous Inputs in Sequential SystemsWhat about external signals?Sequential SystemClockCan’t guaranteesetup and holdtimes will be met!When an asynchronous signal causes a setup/holdviolation...ClockQDITransition is missed onfirst clock cycle, butcaught on next clockcycle.IITransition is caught onfirst clock cycle.?IIIOutput is metastablefor an indeterminateamount of time.Q: Which cases are problematic?6.111 Fall 2007 Lecture 6, Slide 9Asynchronous Inputs in Sequential SystemsAll of them can be, if more than one happenssimultaneously within the same circuit.Idea: ensure that external signals directly feedexactly one flip-flopD QSequential SystemClockThis prevents the possibility of I and II occurring in different placesin the circuit, but what about metastability?D QD QQ0ClockClockQ1Async InputClocked Synchronous System6.111 Fall 2007 Lecture 6, Slide 10Handling Metastability• Preventing metastability turns out to be an impossible problem• High gain of digital devices makes it likely that metastableconditions will resolve themselves quickly• Solution to metastability: allow time for signals to stabilizeHow many registers are necessary?• Depends on many design parameters(clock speed, device speeds, …)• In 6.111, a pair of synchronization registers is sufficientD QComplicatedSequential LogicSystemClockD QD QCan bemetastableright aftersamplingVery unlikely to bemetastable for >1clock cycleExtremely unlikely tobe metastable for >2clock cycle6.111 Fall 2007 Lecture 6, Slide 11III. Finite State Machines• Finite State Machines (FSMs) are a useful abstraction forsequential circuits with centralized “states” of operation• At each clock edge, combinational logic computes outputs andnext state as a function of inputs and present stateCombinationalLogicFlip-FlopsQDCLKinputs+presentstateoutputs+nextstatenn6.111 Fall 2007 Lecture 6, Slide 12Example 1: Light SwitchLIGHT= 0LIGHT= 1BUTTON=1BUTTON=1BUTTON=0 BUTTON=0• State transition diagramD QBUTTONLIGHTCLK01Combinational logicRegister• Logic diagram6.111 Fall 2007 Lecture 6, Slide 13Example 2: 4-bit Counter+1clkcount44• Logic diagram# 4-bit counter module counter(clk, count); input clk; output [3:0] count; reg [3:0] count; always @ (posedge clk) begin count <= count+1; endendmodule• Verilog6.111 Fall 2007 Lecture 6, Slide
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