L9: 6.111 Spring 2004 1Introductory Digital Systems LaboratoryL9: Analog Building BlocksL9: Analog Building Blocks((OpAmpsOpAmps, A/D, D/A), A/D, D/A)Acknowledgement: Dave WentzloffL9: 6.111 Spring 2004 2Introductory Digital Systems LaboratoryIntroduction to Operational AmplifiersIntroduction to Operational Amplifiers Typically very high input resistance ~ 300KΩ High DC gain (~105) Output resistance ~75ΩDC ModelLM741 PinoutinoutVfaV ⋅= )(a(f)f10Hz105-20dB/decade+10 to +15V-10 to -15Vidva⋅idvinRoutR+−outvL9: 6.111 Spring 2004 3Introductory Digital Systems LaboratoryThe Inside of a 741 The Inside of a 741 OpAmpOpAmpDifferentialInput StageAdditionalGain StageOutput StageCurrent Source for biasingBipolar versionhas small inputBias currentMOS OpAmpshave ~ 0 input currentGain is Sensitive to Operating Condition (e.g., Device, Temperature, Power supply voltage, etc.)Output devicesprovides largedrive currentL9: 6.111 Spring 2004 4Introductory Digital Systems LaboratorySimple Model for an Simple Model for an OpAmpOpAmp+-i+~ 0i-~ 0+-+-vidvoutvoutvidVCC= 10V-VCC= -10Vε = 100µV-100µVReasonable approximation+-vid+-avid+-voutLinear Mode If -VCC< vout< VCC+-vid-VCC+-voutNegative Saturationvid< - ε-++-vid+-voutPositive Saturationvid> ε-++VCC-VCCVCCSmall input range for “Open” loop ConfigurationL9: 6.111 Spring 2004 5Introductory Digital Systems LaboratoryThe Power of (Negative) FeedbackThe Power of (Negative) Feedbackinvoutv1R2R-+-+vid+-avid+-voutinvR2-+R1021=+++RvvRvvidoutidinavvoutid=⎥⎦⎤⎢⎣⎡++−=221111RRaRavRvoutin()()1112212>>−≈++−= aifRRRRaaRvvinout Overall (closed loop) gain does not depend of open loop gain Trade gain for robustness Easier analysis approach: “virtual short circuit approach” v+= v-= 0 if OpAmp is linear+-L9: 6.111 Spring 2004 6Introductory Digital Systems LaboratoryBasic Basic OpAmpOpAmpCircuitsCircuitsinvoutv2R1RinRRRoutvv121+≈+−1invoutv2inv1R1R2R2R()1212ininRRoutvvv −≈Voltage Follower (buffer)Non-invertingDifferential Inputinvoutvinoutvv≈invoutvRC∫∞−−≈tinRCoutdtvv1Integrator+-L9: 6.111 Spring 2004 7Introductory Digital Systems LaboratoryUse With Open LoopUse With Open LoopAnalog Comparator:Is V+ > V- ?The Output is a DIGITAL signalLM311 is a single supplycomparatorL9: 6.111 Spring 2004 8Introductory Digital Systems LaboratoryData Conversion: Quantization NoiseData Conversion: Quantization Noise Quantization noise exists even with ideal A/D and D/A convertersinvnoisevLSBA/D D/AdigitalcodeinvQuantizationnoise+−00 01 101104refV2refV43refVBinary codeAnalog Output0001101104refV2refV43refVAnalog InputBinary OutputrefV4refV2refV43refVrefVA/D ConversionD/A ConversionL9: 6.111 Spring 2004 9Introductory Digital Systems LaboratoryNonNon--idealities in Data Conversionidealities in Data ConversionBinary codeAnalogIdealOffseterrorBinary codeAnalogIdealGainerrorOffset – a constant voltage offset that appears at the output when the digital input is 0Gain error – deviation of slope from ideal value of 1Binary codeAnalogIdealIntegralnonlinearityIntegral Nonlinearity – maximum deviation from the ideal analog output voltageDifferential nonlinearity – the largest increment in analog output for a 1-bit changeBinary codeAnalogIdealNon-monoticityL9: 6.111 Spring 2004 10Introductory Digital Systems LaboratoryRR--2R Ladder DAC Architecture2R Ladder DAC ArchitectureNote that the driving point impedance (resistance) is the same for each cell. R-2R Ladder achieves large current division ratios with only two resistor values-1L9: 6.111 Spring 2004 11Introductory Digital Systems LaboratoryDAC (AD 558) Specs DAC (AD 558) Specs --Used in Lab 3 Used in Lab 3 8-bit DAC Single Supply Operation: 5V to 15V Integrates required references (bandgap voltage reference) Uses a R-2R resistor ladder Settling time 1µs Programmable output range from0V to 2.56V or 0V to 10V Simple Latch based interfaceL9: 6.111 Spring 2004 12Introductory Digital Systems LaboratoryChip Architecture and InterfaceChip Architecture and InterfaceCECSLATCHD[7:0]Outputs are noisy when input bits settles, so it is best to have inputs stable before latching the input dataL9: 6.111 Spring 2004 13Introductory Digital Systems LaboratorySetting the Voltage RangeSetting the Voltage RangeVery similar to anon-inverting ampStrap output fordifferent voltagerangesConvert data to Offset binaryL9: 6.111 Spring 2004 14Introductory Digital Systems LaboratoryAnother Approach: BinaryAnother Approach: Binary--Weighted DACWeighted DAC Analog Devices AD9768 uses two banks of ratioed currents Additional current division performed by 750 Ω resistor between the two banks Switch binary-weighted currents MSB to LSB current ratio is 2NAD97683b2b1b0bRoutv()0811412213bbbbIRvout+++−=+-I2II4I8Reference current sourceL9: 6.111 Spring 2004 15Introductory Digital Systems LaboratoryGlitchingGlitchingand Thermometer D/Aand Thermometer D/A Glitching is caused when switching times in a D/A are not synchronized Example: Output changes from 011 to 100 – MSB switch is delayed Filtering reduces glitch but increases the D/A settling time One solution is a thermometer code D/A – requires 2N –1 switches but no ratioedcurrents100011→outvtThermometerBinary110011111110010000000TIRoutv()210TTTIRvout++−=II1T2TL9: 6.111 Spring 2004 16Introductory Digital Systems LaboratorySuccessiveSuccessive--Approximation A/DApproximation A/DExample: 3-bit A/D conversion, 2 LSB < Vin< 3 LSB D/A converters are typically compact and easier to design. Why not A/D convert using a D/A converter and a comparator? D to A generates analog voltage which is compared to the input voltage If D to A voltage > input voltage then set that bit; otherwise, reset that bit This type of A to D takes a fixed amount of time proportional to the bit lengthVincodeD/AComparatoroutC+−L9: 6.111 Spring 2004 17Introductory Digital Systems LaboratorySuccessiveSuccessive--Approximation A/DApproximation A/D Serial conversion takes a time equal to N(tD/A+ tcomp)SuccessiveApproximationGeneratorControlDoneGo-+Sample/HoldD/AConvertervinNDataL9: 6.111 Spring 2004 18Introductory Digital Systems LaboratorySuccessiveSuccessive--Approximation A/D Approximation A/D (AD670) (AD670) ––Used in Lab 3Used in Lab 3 ~10µs conversion timeUnipolar (BPO =0)Bipolar (BPO =1)L9: 6.111 Spring 2004 19Introductory Digital Systems LaboratorySingle Write, Single Read OperationSingle
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