6.111 Lecture # 8 Topics for Today: (as time permits)1. Memories2. Assembling 'packages' for designs3. Discussion of design procedure4. Development of a design example using a finite state machinePreview:No class Monday (Student Holiday)Wednesday: quiz rev iew and discussion of Phase IIFriday: Quiz 1Memories are usually organized as 2- dimensional arrays of cellsAddress is split into two parts e.g. 4k = 4096 addresses = 214might have 7 bits of address for each of row and columnConceptual Memory Cell: This is what goes at each intersection of the rowand column lines (i.e. there are a lot of these!)Note how this is like a 'D-Latch' The lines D and D* are from the rowdecoder and control.D = D* = '1' => 'Read': cell contents go onto sense linesD = D* = '0' => This row is not addressed. Output is high (collectorsopen and some other row drives senselines)D = /D* and G = '1': 'Write': D is latched onto cell when G goes lowOutput of this cell is 'opencollector' and so "pullsdown" the sense lines thatgo to the column decodingMUXControl Lines:Often Active LowOE is 'Output Enable'WE is 'Write Enable'CS is 'Chip Select'If: /WE is LOW, /CS is LOW, /OE is HIGH, Data pins are input Input data is written to chipIf /WE is HIGH /CS is LOW /OE is LOW Data pins are output Date is read from memorySome have simpler control structureThe /OE line is in many cases redundant (but having the extra line to use can beconvenient)In these parts,Read => /CS = LOW and /WE = HIGHWrite => /CS = LOW and /WE = LOWRead Cycle TimingAddress takes a little while to propagate into the right placesIt takes a bit less time for the part to 'grab' the output pins(invalid data may be on them initially)And note it takes a little while after /CS goes high for the part to let goof the output pinsAnd if Address goes invalid before /CS goes high, there may be invaliddata on the output pinsWrite cycle timing is a little more complex==> It is most important that Address and Data must BOTH be valid during the write pulse <====> It is also important that Address must be fixed and valid during the Whole of the write pulse <====> Data must be validfor a period at theend of the writepulse <==Tristated or unstableaddress lines can wind upwriting garbage to a largenumber of memorylocations!Here is a general purpose suggestion for handling memory in a FSM controlledsystem.You can do it more simply in Lab 2Driving /CS with /CLK ensures 'clean' write pulses and reduces the possibility ofbus contention. Both WRITE and READ operations are enabled only on thesecond half of the clock cycle (before the positive going edge)This timing diagram illustrates how the scheme on the previous slide might work.It assumes Addr changes after the positive going clock edge and so isstable when the clock is low.Also, if the control lines are driven by a FSM, they will change after thepositive going clock edge too.Packages contain bits (or larger pieces of code) that you may re-use.They are introduced by statements such as:use work.gridpkg.all;To set up a package you first write and test the pieces(perhaps using smaller PLD's than you plan for the actual project to save computationtime) and then:-Assemble all of the generic and port declarations from the entities into a file called (for example) gridpkg.vhd-Then put all of the files into a single file: do something like: cat gridpkg.vhd synchronizer.vhd reg.vhd ctr.vhd fsmt.vhd > all.vhd-Set the device to the target device, C374I.-Compile this file (without it being the Top design).Now you will have something you can use as a library package if you use the parts as specified in theentity declarations.Hierarchical DesignStart with a one-block block diagram.Expand to major blocks.Repeat expansion until blocks are simple.Implement these simple blocks and test.(Code them in VHDL and simulate.)Wire the blocks together.(Use structural instantiation in VHDL.)Test the design.Stay Tuned: we will illustrate these steps.Example: Digitizer Interface, FSM ControlPosition detection using an array of wiresGenerate magnetic field with a coil (not shown here)Count while sweeping over the array (contents of Counter)Detect position of a cursor:By phase reversal Or other artifact of signal detectionv(INT signal)Put count into a register (/LD is low)Implement a 'Handshake'Set handshake line (dav) when signal is readyWait for ready signal (rdy) before counting (SRDY is synchronized RDY)Here is the conventionally drawn FSM diagram of the system we are going toimplement:States:Ready: waiting for the synchronized RDYsignal from the user (_ of handshake)Count: counter is incrementing itself alongwith the position sensor of the gridERR: Counter has overflowed, which meanssensor was not foundLoad: Counter was interrupted by findingthe sensor: contents (count) is the positionCount is loaded onto output counterReset: transient state - counter is clearedand transition is made to ReadyI/O Signals for FSMInput:SRDY Synchronized GO (receiver ready)INT Grid position is detected (assumed synchronized )ERR Grid overflow (position not detected)Output:DAV Data is readyLD Load count into the output registerCLR Clear the counterCOUNT Enable the counter to countOne smaller of the blocks is the syhchronizer:library ieee;use ieee.std_logic_1164.all;entity synchronizer is port (rdy, clk : in std_logic; srdy : out std_logic);end synchronizer;architecture behavioral of synchronizer isbegin -- behavioral sync:process(clk) begin if rising_edge(clk) then srdy <= rdy; end if; end process sync;end architecture behavioral;Second Part: This is a loadable register whose width is a generic.size has a default - one number to changeinstantiation as a component can define sizelibrary ieee;use ieee.std_logic_1164.all;entity reg is generic (size: integer := 4); port (n_ld, clk : in std_logic; grid : in std_logic_vector(size - 1 downto 0); data : out std_logic_vector(size - 1 downto 0));end reg;architecture behavioral of reg isbegin -- behavioral regff:process(clk) begin if rising_edge(clk) then if n_ld = '0' then data <= grid; end if; end if; end process;end architecture behavioral;Now we are going to test the resister, using a counter which we have already designedand will discuss next.library ieee;use ieee.std_logic_1164.all;use work.gridpkg.all;entity testreg is
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