L12: 6.111 Spring 2009 1Introductory Digital Systems LaboratoryL12: Reconfigurable Logic ArchitecturesL12: Reconfigurable Logic ArchitecturesAcknowledgements:¾ Lecture material adapted from R. Katz, G. Borriello, “Contemporary Logic Design”(second edition), Copyright 2005 Prentice-Hall/Pearson Education. ¾ Frank Honore¾Lecture Notes prepared by Professor Anantha ChandrakasanL12: 6.111 Spring 2009 2Introductory Digital Systems LaboratoryHistory of Computational FabricsHistory of Computational Fabrics Discrete devices: relays, transistors (1940s-50s) Discrete logic gates (1950s-60s) Integrated circuits (1960s-70s) e.g. TTL packages: Data Book for 100’s of different parts Gate Arrays (IBM 1970s) Transistors are pre-placed on the chip & Place and Route software puts the chip together automatically – only program the interconnect (mask programming) Software Based Schemes (1970’s- present) Run instructions on a general purpose core Programmable Logic (1980’s to present) A chip that be reprogrammed after it has been fabricated Examples: PALs, EPROM, EEPROM, PLDs, FPGAs Excellent support for mapping from Verilog ASIC Design (1980’s to present) Turn Verilog directly into layout using a library of standard cells Effective for high-volume and efficient use of silicon areaL12: 6.111 Spring 2009 3Introductory Digital Systems LaboratoryLisp MachineL12: 6.111 Spring 2009 4Introductory Digital Systems LaboratoryReconfigurable LogicReconfigurable Logic Logic blocks To implement combinationaland sequential logic Interconnect Wires to connect inputs andoutputs to logic blocks I/O blocks Special logic blocks at periphery of device forexternal connections Key questions: How to make logic blocks programmable?(after chip has been fabbed!) What should the logic granularity be? How to make the wires programmable?(after chip has been fabbed!) Specialized wiring structures for localvs. long distance routes? How many wires per logic block?LogicLogicConfigurationInputsOutputsnmQQSETCLRDL12: 6.111 Spring 2009 5Introductory Digital Systems LaboratoryProgrammable Array Logic (PAL)Programmable Array Logic (PAL) Based on the fact that any combinational logic can be realized as a sum-of-products PALs feature an array of AND-OR gates with programmable interconnectinputsignalsoutputsignalsprogramming of product termsprogramming of sum termsANDarrayOR arrayL12: 6.111 Spring 2009 6Introductory Digital Systems LaboratoryInside the 22v10 PALInside the 22v10 PAL Each input pin (and its complement) sent to the AND array OR gates for each output can take 8-16 product terms, depending on output pin “Macrocell” block provides additional output flexibility...L12: 6.111 Spring 2009 7Introductory Digital Systems LaboratoryCypress PAL CE22V10Cypress PAL CE22V10Combinational/active lowCombinational/active high Outputs may be registered or combinational, positive or invertedFrom Lattice SemiconductorFrom CypressL12: 6.111 Spring 2009 8Introductory Digital Systems LaboratoryRAM Based Field Programmable RAM Based Field Programmable Logic Logic --XilinxXilinxCLBCLBCLBCLBSwitchMat rixProgrammableInterconnectI/O Blocks (IOBs)ConfigurableLogic Blocks (CLBs)D QSlewRateControlPassivePull-Up,Pull-DownDel ayVccOutputBufferInputBufferQ DPad DQSDRDECS/RContr olDQSDRDECS/RContr ol11F'G'H'DINF'G'H'DINF'G'H'H'HFunc.Gen.GFunc.Gen.FFunc.Gen.G4G3G2G1F4F3F2F1C4C1C2C3 KYX H1 DIN S/R ECL12: 6.111 Spring 2009 9Introductory Digital Systems LaboratoryThe The XilinxXilinx4000 CLB4000 CLBL12: 6.111 Spring 2009 10Introductory Digital Systems LaboratoryTwo 4Two 4--input Functions, Registered Outputinput Functions, Registered Outputand a Two Input Functionand a Two Input FunctionL12: 6.111 Spring 2009 11Introductory Digital Systems Laboratory55--input Function, Combinational Outputinput Function, Combinational OutputL12: 6.111 Spring 2009 12Introductory Digital Systems LaboratoryLUT MappingLUT Mapping N-LUT direct implementation of a truth table: any function of n-inputs. N-LUT requires 2Nstorage elements (latches) N-inputs select one latch location (like a memory)4LUT exampleLatches set by configuration bitstreamInputsOutputWhy Latches and Not Registers?L12: 6.111 Spring 2009 13Introductory Digital Systems LaboratoryConfiguring the CLB as a RAMConfiguring the CLB as a RAMMemory is built using Latches not FFsRead is same a LUT Function!16x2L12: 6.111 Spring 2009 14Introductory Digital Systems LaboratoryXilinxXilinx4000 Interconnect4000 InterconnectL12: 6.111 Spring 2009 15Introductory Digital Systems LaboratoryXilinxXilinx4000 Interconnect Details4000 Interconnect DetailsWires are not ideal!L12: 6.111 Spring 2009 16Introductory Digital Systems LaboratoryXilinxXilinx4000 Flexible IOB4000 Flexible IOBAdjust Transition TimeAdjust the Sampling EdgeOutputs through FF or bypassedL12: 6.111 Spring 2009 17Introductory Digital Systems LaboratoryAdd Bells & WhistlesAdd Bells & WhistlesHardProcessor I/OBRAMGigabit SerialMultiplierProgrammableTerminationZVCCIOZZImpedanceControlClockMgmt (DCM)18 Bit18 Bit36 BitCourtesy of David B. Parlour, ISSCC 2004 Tutorial, “The Reality and Promise of Reconfigurable Computing in Digital Signal Processing”L12: 6.111 Spring 2009 18Introductory Digital Systems LaboratoryThe The VirtexVirtexII CLB (Half Slice Shown)II CLB (Half Slice Shown)L12: 6.111 Spring 2009 19Introductory Digital Systems LaboratoryAdder ImplementationAdder ImplementationY = A ⊕ B ⊕ CinABCinCoutLUT: A⊕B1 half-Slice = 1-bit adderDedicated carry logicL12: 6.111 Spring 2009 20Introductory Digital Systems LaboratoryCarry ChainCarry Chain1 CLB = 4 Slices = 2, 4-bit adders64-bit Adder: 16 CLBs+CLB15CLB0A[3:0]B[3:0]A[63:60]B[63:60]A[63:0]B[63:0]Y[63:0]Y[3:0]Y[63:60]Y[64]CLBs must be in same columnCLB1A[7:4]B[7:4]Y[7:4]L12: 6.111 Spring 2009 21Introductory Digital Systems LaboratoryVirtexVirtexII FeaturesII FeaturesDouble Data Rate registersDigital Clock ManagerEmbedded MultiplierBlock SelectRAML12: 6.111 Spring 2009 22Introductory Digital Systems LaboratoryThe Latest Generation: VirtexThe Latest Generation: Virtex--664 (18x18)72kbit15kbit240Spartan 3E1,344 (25x18)22,752kbit6,200kbit667,000Virtex 6*144 (18x18)2,592kbit1,056kbit8,448Virtex 2*MultipliersBlock RAMDist RAMCLB* Compare 2ndmost performanceDSP with 25x18 multiplierGigabit ethernetsupportL12: 6.111 Spring 2009 23Introductory Digital Systems LaboratoryDesign Flow Design
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