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FPGA videogame 6.111 final project report Telmo Luis Correa Junior2 Index Index .................................................................................................................................2 List of figures ....................................................................................................................3 List of tables...................................................................................................................... 4 Introduction .......................................................................................................................5 Project Design ...................................................................................................................6 Design tools................................................................................................................... 6 Design overview ............................................................................................................7 Output........................................................................................................................7 GPU communication..................................................................................................9 GPU submodules...................................................................................................... 10 Hardware protocols...................................................................................................... 12 CPU to GPU ............................................................................................................12 Blob manager to blob............................................................................................... 17 Feedback ......................................................................................................................... 18 References ....................................................................................................................... 19 Appendix A: Verilog files................................................................................................ 20 final-project.v .............................................................................................................. 20 vga.v............................................................................................................................ 34 beta2.v ......................................................................................................................... 35 coordinate_generator.v................................................................................................. 41 debounce.v................................................................................................................... 42 blob.v........................................................................................................................... 42 blob_manager.v............................................................................................................ 48 sprite_manager.v.......................................................................................................... 52 pixel_tree.v.................................................................................................................. 59 pixel_combinator.v ...................................................................................................... 66 interrupt_generator.v.................................................................................................... 68 fifo.v............................................................................................................................ 71 Appendix B: Bsim macros ............................................................................................... 73 beta.uasm..................................................................................................................... 73 ram.uasm ..................................................................................................................... 84 Appendix C: Other scripts.............................................................................................. 100 ImageConverter.java.................................................................................................. 100 betamem.py ............................................................................................................... 101 Appendix D: ROM Sprites............................................................................................. 1043 List of figures Fig. 1: System block diagram ............................................................................................ 8 Fig. 2: VGA horizontal sync ............................................................................................. 9 Fig. 3: VGA vertical sync ................................................................................................. 9 Fig. 4: GPU block diagram .............................................................................................. 114 List of tables Table 1: VGA timings........................................................................................................ 9 Table 2: Blob states ......................................................................................................... 12 Table 3: Blob pixel filters ................................................................................................ 16 Table 4: command_bus protocol ..................................................................................... 185 Introduction The aim of this project was to develop a gaming system on the FPGA easily reconfigurable; by switching small component parts on the system, it could be used to play another game. Two apparently opposing goals were set: to avoid hardwiring game logic into the hardware, and to use the massive parallel processing power available on the labkit to speed up the game, making this project have an interesting digital design aspect. The compromise was achieved by designing the game logic itself to be controlled by a microprocessor, but letting the graphics processing being controlled by hardware, in the form of a somewhat primitive graphics processing unit. Diverse factors, such as availability, familiarity and available technical support, the microprocessor architeture chosen was the Beta, a processor used for an introductory computational structures class at MIT, 6.004. The GPU design
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