1Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 – Introductory Digital Systems Laboratory ModelSim/Verilog Tutorial Authors: David Milliner, Frank Honoré, Spring, 2004 Jenny Lee, Spring, 2005 * There have been some important changes to this document, which are indicated by underlining. If you have already read this document, please read at least the underlined parts. The newly added/modified sections are What are Library and Project, Creating Files in ModelSim, and Wave Window, and Useful Buttons and Command Lines. Introduction This tutorial is designed to familiarize you with Verilog coding/syntax and simulation in the ModelSim environment. Verilog HDL is a hardware description language used to design digital systems. Along with VHDL, Verilog is the primary industry tool for programming digital systems. ModelSim is the industry standard simulation tool for verifying digital designs. Directory Structure When you log into the lab computers you will have access to your own drive (U:/) and a directory in the local drive (E:/) where you can store your files for this class. For ModelSim to operate correctly, you must store all your source files (*.v) in E:/Documents and Settings/[Athena Username]/Desktop or equivalently on the Desktop of your local machine. This directory is linked directly to U:/Desktop, but please make sure you use source files stored in E:/ directory rather than U:/Desktop when using ModelSim. Although this directory is accessible from any computers in the lab area, you will probably want to back these files up on your Athena account from time to time. You can transfer files back and forth from your Athena account using WinSCP. On the Desktop of your local computer, create a tutorial folder with the subfolders src and sims. The src folder will contain the source codes for this tutorial and the sims directory is where you will be compiling your code. On the lab PCs you will see a shared drive (S:/) from which you should be able to access the files necessary for this tutorial. Copy the files from the S:/6.111/tutorial2/ folder to your src folder on your Desktop. The files to copy are counter.v, top.v, tb_tutorial.v, full_adder.v, full_adder_4bit.v, and test_adder.v. Verilog Source Code and Testbench The file counter.v is a simple two-bit Verilog counter designed to divide the input clock by four. This counter is designed to reset back to zero on the positive assertion of the reset signal. Your counter is instantiated in the top level file top.v. The file tb_tutorial.v is used to simulate the counter module in counter.v. We recommend you spend a few minutes familiarizing yourself with this code and the Verilog syntax.2Opening ModelSim You can access ModelSim either through the PCs in the lab or an Athena Sun Workstation. On the Lab PC under Windows XP, launch ModelSim from the Desktop icon (or Start > All Programs > ModelSim SE > ModelSim). If it’s your first time opening ModelSim or if you encounter problems with licenses, you can run the license wizard: Start > All Programs > ModelSim SE > Licensing Wizard. The license file should be set to ‘[email protected]’. On Athena Sun workstation, first run 'setup 6.111' to configure your environment correctly. Then run 'vsim &' to start the application. Online help and tutorials for ModelSim are available from the Help pull-down menu. Help > SE PDF Documentation > Tutorial will bring up the guide for a recommended tutorial. The PDF for the user's manual is also available on the course website: Software Tools > Verilog Simulation. (must have MIT certificates). What are Library and Project? Before jumping into using ModelSim, there are two important components you should get familiar with: Library and Project. Library provides an environment for you to compile and simulate your design, while Project provides you a place to contain all relevant files and settings for independent design including its working library. Library: A directory that contains compiled design units, such as modules. There are two types of libraries: Resource Library and Working Library: Resource Library: contains static contents, such as the compiled version of standard modules. Resource libraries, such as ieee, can be found in the ‘library’ pane on the left-hand side of ModelSim. Working Library: contains the compiled version of your design. The contents of a working library change every time you compile your design. The default working library in ModelSim is named work and is predefined in the ModelSim compiler. The working library when created or linked to your source code can be accessed through the ‘library’ pane on the left-hand side of ModelSim. Project: A collection of various files for designs under test, such as Verilog source files, local working libraries, references to resource libraries, and simulation configuration (*.mpf files).3Creating files in ModelSim There are two ways to start creating your designs in ModelSim: 1.Creating a project or 2.Opening or creating a Verilog file without a project. 1. Creating a project Create a new project: File > New > Project Specify your project name and specify the Project Location as a directory under E:\Documents and Settings\[username]\Desktop. Leave the Default Library Name to work. Now, you have created a project .mpf file and a working library, which can store useful information, such as your simulation configuration, for future use. Now, add items to your project by either creating a new Verilog source file or adding an existing file. 2. Creating without a project: Create a new file: File > New > Source > Verilog or open an existing Verilog file: File > Open > File. To compile the source files in the ModelSim environment, you must create a working directory or map an existing working directory: File > New > Library or File > Import > Library or type ‘vlib work’ in the command line window. As a good design practice, we recommend you to follow the first option: creating a new project. For Verilog files required for labs and psets, create a new project such as ‘lab01’ or ‘pset03’ under the default work library as its working library, because you do not explicitly need to specify the work library when compiling. For the final project, which contains many layers of hierarchy, create a new project under a new working library, such as ‘final_proj’. For this tutorial,
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