Figure 1: Diagram for intersection with corresponding lights.Table 1: Default Timing Parameters.Figure 2: Diagram for intersection with corresponding lights.Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory (Spring 2006) Laboratory 2 (Traffic Light Controller) Check Off Sheet Student Name: TA Signature/Date: Must Show to TA at beginning of Chekoff • FSM State Transition Diagram • Verilog Code Printout Be Able to Demonstrate Your Working Lab • You will be first asked to demonstrate regular operation with default values • You will be asked to reprogram your time values and continue operation • You will be asked to demonstrate functionality of Walk Request Register • You will be asked to demonstrate functionality of the side sensor Be Able to Respond to any of the Following Questions (and possibly others). You will likely be asked two questions from the following by a TA • What could happen if an input were not synchronized to the clock? • Describe your synchronizer module and why it is important. • Describe your walk request register. • Describe your divider module. • What is the difference between a Moore and a Mealy machine? • Describe the design flow for your Traffic Light Controller. 1Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory Laboratory 2 - Traffic Light Controller (Spring 2006) Issued: February 22, 2006 Checkoff Due: March 6, 2006 Report Due: March 8, 2006 Introduction In this lab you will implement a traffic light controller that operates main street, side street and walk lamps. You will be using a finite state machine to implement this controller. This lab pro-vides you with a design methodology that will be useful in future labs and final projects. This involves planning your design, coding, wiring, and debugging your design. Procedure There are two major phases. The first is the design phase, which consists of reading through the lab, planning, and coming up with a design. Although not required, it is suggested that you sched-ule a conference with a member of the teaching staff to review your design. This will help catch any major mistakes early in the process. The next phase is to implement the lab using the FPGA. After you verify the traffic light control-ler’s functionality, you can get checked off. Be ready to demonstrate the lab, and be ready to present solutions for the problems asked in the checklist. You will be required to write a detailed report (see guidelines for lab 2 report at the end). Traffic Light Controller Description The traffic light controller is for an intersection between a Main Street and a Side Street. Both streets have a red, yellow, and green signal light. Pedestrians have the option of pressing a walk button to turn all the traffic lights red and cause a single walk light to illuminate. Lastly, there is a sensor on the Side Street which tells the controller if there are cars still on the Side Street. This is summarized in Figure 1. You may assume that the 4 walk buttons placed at each street corner are hooked into the traffic light controller using a wired-OR. For this reason, you may assume that the controller only needs a single input called Walk-Request. 2SideSensor rm ym gm walk rs ys gs Main Street Street Walk lamp Side light Main light Walk Button Figure 1: Diagram for intersection with corresponding lights. Table 1: Default Timing Parameters. Interval Name Symbol Parameter Number Default Time (sec) Time Valu e Base Interval tBASE 00 6 0110 Extended Interval tEXT 01 3 0011 Yellow Interval tYEL 10 2 0010 The side street sensor is placed near the intersection to tell the controller when there are cars pass-ing over the sensor. You may assume the sensor remains constantly high if several cars pass over the sensor, rather than quick pulses, provided the cars are close enough together. You do not need to implement this specific functionality. This input is named Sensor. The traffic lights are timed on three parameters (in seconds), the base interval (tBASE), the extended interval (tEXT), and the yellow light interval (tYEL). The default values listed in Table 1 are to be loaded into registers in the FPGA on reset, and may be reprogrammed on demand using switches and buttons on your kit with the Time_Parameter_Selector, Time_Value, and Repro-gram signals. Time_Parameter_Selector uses the Parameter Number code to select the interval during programming. Time_Value is a 4-bit value representing the value to be programmed; there-3fore, it has a duration of seconds between 0 and 15. The Reprogram button tells the system to set the currently selected interval to Time_Value. The operating sequence of this intersection begins with the Main Street having a green light for 2 lengths of tBASE seconds. Next, the Main lights turn to yellow for tYEL, and switches to the Side Street green light. The Side street is green for tBASE, and its yellow is held for tYEL. Whenever a stoplight is green or yellow, the other street’s stoplight is red. Under normal circumstances, this cycle repeats continuously. There are two ways the controller can deviate from the typical loop. First, a walk button allows pedestrians to submit a walk request. The internal Walk Register should be set on a button press and the controller should service the request after the Main street yellow light by turning all lights to red, and the walk light to on. After a walk of tEXT seconds, the traffic lights should return to its usual routine by turning the Side Street green. The walk button should be ignored during the walk service. The second deviation is the traffic sensor. If the traffic sensor is high at the end of the first tBASE length of the Main street green, the light should remain green only for an additional tEXT seconds, rather than the full tBASE. Additionally, if the traffic sensor is high during the end of the Side Street green, it should remain green for an additional tEXT seconds. Block Descriptions/Implementation You will be implementing this lab by programming each block individually and then instantiating and connecting the Verilog modules together in the top level lab2_labkit.v module. Synchronizer On the block diagram, you see that all input signals pass through the synchronizer before going to other blocks. The
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