1Name: Date:TA:Lab 1: Checkoff SheetBe prepared to show relevant diagrams as requested in each problem. You may get checked offper problem, rather than the whole lab at once. Collect initials for each problem on this sheet andturn it in with your report.1. _____________2. _____________3. _____________4. _____________5. _____________6. _____________7. _____________2Name: Date Submitted:TA:Lab 1: Report TemplateThis report template is useful to prepare for each exercise’s checkoff. Fill in answers for the ques-tions requested by exercise; you may use a different sheet of paper if more convenient, but be sureto follow the template. Be sure to prepare relevant diagrams as requested by each problem. Turnin this report after completing the lab 1 checkoff.Exercise 1: TTL/CMOS Static Electrical CharacteristicsLow Voltage Measurement (In = 1) for 74LS00: High Voltage Measurement (In = 0) for 74LS00: Low Voltage Measurement (In = 1) for 74HC00: High Voltage Measurement (In = 0) for 74HC00:For each of these measurements, does the output satisfy the ranges specified in the appropriatedatasheets? Explain.What problems could arise from using the LS series with the HC series (at +5V supply)?3Exercise 2: Build your own ring oscillatorPlease draw out the waveform showing the output for the 5-inverter oscillator ring. Be sure tolabel the maximum and minimum voltages, and label the appropriate time intervals.What is the average TTL inverter propagation delay? Show calculations and briefly explain.Estimate the period of oscillation for a 3 inverter ring, rather than 5? Explain. What was yourmeasured result?4What happens if you add a long piece of wire to the 3 inverter ring? Explain what causes this tohappen.What is the voltage measurement when you connect the output to the input of a single inverter?What is the significance of this voltage?Exercise 3: GlitchesWhat is the length of the glitch measured in this exercise? Why does this glitch occur, and what is the lesson learned from this exercise? Under what conditions is it a bad idea to use a glitchy signal as an input?5Exercise 4: Asynchronous CountersPlease draw a diagram showing the flip-flop arrangement of a typical asynchronous counter,emphasizing the source of each clk input for each flip-flop.What is your measurement for the clk to MSB delay? From this measurement, show calculationsfor the clk-to-q delay for a typical flip-flop in the LS393, and explain the derivation.6Exercise 5: Synchronous CounterDraw a diagram showing the flip-flop arrangement of a typical synchronous counter, emphasizingthe source of each clk input for each flip-flop.Explain how the RCO signal of the low-order counter is used to control the high-order counter.How long does it take, after the rising edge of the clock, for the A output to change state? For theB output to change state? Explain why they are the same/different.Show your logic analyzer trace of the A, B, C, D and RCO outputs to the TA. Can you observeany glitches on RCO? Explain under what circumstance you might expect RCO glitches to occur.7Explain some differences between the 74LS163 and the 74LS393 in terms of design and perfor-mance. How many flip-flops and how much logic is required to implement the counter?Exercise 6: Designing Combinational LogicDraw out the 7 Karnaugh maps corresponding to the different outputs, and circle the implicantsthat generate the Minimal Sum of Products equation. Write down the MSOP equations beloweach Karnaugh map. Be sure to label each Karnaugh map with the appropriate segment. 0 101 0 101 0 101 0 101 0 101 0 101 0 1018Using only inverters (74LS04) and 2-input NAND gates (74LS00), draw a schematic that imple-ments the equations above. Add pin numbers to your diagram and then implement it on your pro-toboard. What’s the propagation delay of your circuit?Exercise 7: Writing Verilog CodePrint out your code for your LS163 module and staple it to this this Checkoff
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