6.111 Fall 2006 Lecture 15, Slide 16.111 Lecture 15Today: Video1.Cathode Ray Tubes2.NTSC3.Video Decode/Encode4.VGA Video5.Demo6.111 Fall 2006 Lecture 15, Slide 21. The CRT: Generalized Video DisplayThink of a color video display as a 2D grid of picture elements (pixels). Each pixel is made up of red, green and blue (RGB) emitters. The relative intensities of RGB determine the apparent color of a particular pixel.One pixelH pixels/lineV lines/frameTraditionally H/V = 4/3 or with the advent of high-def 16/9.Lots of choices for H,V and display technologies (CRT, LCD, …) Okay, but how do I send an image to a display?6.111 Fall 2006 Lecture 15, Slide 3Background: Cathode Ray TubesSource: PixTechPhosphor Screen: emits light when excited by electron beam, intensity of beam determines brightnessAnodeCathode: separate beams for R, G and BShadow mask: ensures R beam only illuminates R pixels, etc.Deflection coil (aka yoke): magnetically steers beam in a left-to-right top-to-bottom pattern. There are separate H and V coils.6.111 Fall 2006 Lecture 15, Slide 4Deflection WaveformsSource: Xilinx Spartan-3 Starter Kit Board User Guide6.111 Fall 2006 Lecture 15, Slide 5Sync Signals (HS and VS)6.111 Fall 2006 Lecture 15, Slide 6Sync Signal TimingThe most common ways to send an image to a video display (even displays that don’t use deflection coils, eg, LCDs) require you to generate two sync signals: one for the horizontal dimension (HS)and one for the vertical dimension (VS).Pulse widthTPWBack porch TBPFront porch TFPDisplay time TDISPPeriod TPFormat CLK P PW BP DISP FPVGA HS (pixels) 25Mhz 794 95 47 640 13VS (lines) -- 528 2 33 480 13XGA HS (pixels) 65Mhz 1344 136 160 1024 24VS (lines) -- 806 6 23 768 96.111 Fall 2006 Lecture 15, Slide 7InterlaceNon-interlaced (aka progressive) scanning:– VS period is a multiple of HS period– Frame rate >= 60Hz to avoid flickerInterlaced scanning:VS period is nota multiple of HS period, so successive vertical scan are offset relative to horizontal scan, so vertical position of scan lines varies from frame to frame.NTSC example:•525 total scan lines (480 displayed)•2 fields of 262.5 scan lines (240 displayed). Field rate is 60Hz, frame rate = 30Hz6.111 Fall 2006 Lecture 15, Slide 82. NTSC*: Composite Video Encoding100 IRE = 1.0VSource: http://www.ntsc-tv.com*National Television System Committee: 19403.579545 MHz“colorburst”6.111 Fall 2006 Lecture 15, Slide 93. Video Capture: Signal Recovery• Composite video has picture data and both syncs.– Picture data (video) is above the sync level. – Simple comparators extract video and composite sync.• Composite sync is fed directly to the horizontal oscillator.• A low-pass filter is used to separate the vertical sync.– The edges of the low-passed vertical sync are squared up by a Schmidt trigger.Sync Level+−+−To extract horizontaland vertical synchronizationfrom composite videoLPFVideo SignalComposite Sync: toHorizontal OscillatorTo VerticalOscillatorVideoComposite6.111 Fall 2006 Lecture 15, Slide 10Labkit: ADV7185 NTSC Decoder• Decodes NTSC and PAL video (composite or S-video) • Produces CCIR656 (10-bit) or CCIR601 (8-bit) digital data6.111 Fall 2006 Lecture 15, Slide 11Labkit: ADV7185 NTSC Decoder• Decodes NTSC and PAL video (composite or S-video) • Produces CCIR656 (10-bit) or CCIR601 (8-bit) digital data• YUV: Y=brightness, U & V = color ; CB→ U, CR→ VR = Y + 1.402 VG = Y – 0.344 U – 0.714 VB = Y + 1.772 U6.111 Fall 2006 Lecture 15, Slide 12Labkit: AD7194 Digital Video EncoderCCIR 601/656 4:2:2 digital video data → analog baseband TV signal6.111 Fall 2006 Lecture 15, Slide 134. VGA VideoHorizBlankingVideoLine25.17 μsHoriz.Sync26.11 μs29.88 μs31.77 μsVerticalBlankingVideoFrame15.25 msVert.Sync15.70 ms15.764 ms16.784 ms6.111 Fall 2006 Lecture 15, Slide 14• Two Challenges:Labkit: ADV7125 Triple DAC (VGA)• (1) Generate Sync Signals• Sync signal generation requires precise timing• Labkit comes with 27 MHz clock• Use phase-locked-loops (PLL) to create higher frequencies• Xilinx FPGA’s have a “Digital Clock Manager” (DCM)DCM pixel_clock (.CLKIN(clock_27mhz), .CLKFX(pixel_clock);// synthesis attribute CLKFX_DIVIDE of pixel_clock is 10// synthesis attribute CLKFX_MULTIPLY of pixel_clock is 2427 MHz * 24 / 10 = 64.8 MHz→ Used in Lab5!• (2) Generate Video Pixel Data (RGB)• Use ADV7125 Triple DAC• Send 24 bits of R,G,B data atpixel clock rate to chip• Create pixels either in real time• Or using dual port RAM• Or from character maps• Or …?6.111 Fall 2006 Lecture 15, Slide 15Generating VGA-style VideoSyncGenerationPixelLogicVideomemoryColorLookupTable(optional)DACHSVSRAGABARDGDBDCPUPixel CLKHpos, Vpos, blankingWith color lookup table, pixel data is used as an index to lookup R,G,B color value.Without color lookup table, pixel data is used directly as R,G,B value (aka “true color”)dataaddr6.111 Fall 2006 Lecture 15, Slide 16Simple VGA Interface for FPGAYour circuitry should produce TTL-level signals (3.3V high level)HS, VS are active-low signals.R, G, B are active-high.Shown: a simple “8-color”schemeThe R, G and B signals are terminated with 75 Ohms to ground inside of the VGA monitor. So when you drive your 3.3V signal through the 270 Ohm series resistor, it shows up at the monitor as 0.7V – exactly what the VGA spec calls for.)3.3)(2707575(7.0 VV+=Poor man’s Video DAC6.111 Fall 2006 Lecture 15, Slide 17module xvga(clk,hcount,vcount,hsync,vsync);input clk; // 64.8 Mhzoutput [10:0] hcount;output [9:0] vcount;output hsync, vsync;output [2:0] rgb;reg hsync,vsync,hblank,vblank,blank;reg [10:0] hcount; // pixel number on current linereg [9:0] vcount; // line numberwire hsyncon,hsyncoff,hreset,hblankon; // next slide for generationwire vsyncon,vsyncoff,vreset,vblankon; // of timing signalswire next_hb = hreset ? 0 : hblankon ? 1 : hblank; // sync & blankwire next_vb = vreset ? 0 : vblankon ? 1 : vblank;always @(posedge clk) beginhcount <= hreset ? 0 : hcount + 1;hblank <= next_hb;hsync <= hsyncon ? 0 : hsyncoff ? 1 : hsync; // active lowvcount <= hreset ? (vreset ? 0 : vcount + 1) : vcount;vblank <= next_vb;vsync <= vsyncon ? 0 : vsyncoff ? 1 : vsync; // active lowendVerilog:XVGA Display(1024x768)6.111 Fall 2006 Lecture 15, Slide 18XVGA (1024x768) Sync Timing// assume 65 Mhz pixel clock// horizontal: 1344 pixels
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