6.111 Fall 2007 Lecture 11, Slide 11. Operational Amplifiers: an Introduction• Typically very high inputresistance ~ 300KΩ• High DC gain (~105)• Output resistance ~75ΩDC ModelinoutVfaV != )(a(f)f10Hz105-20dB/decadeLM741 Pinout+10 to +15V-10 to -15Vidva⋅idvinRoutR+−outv6.111 Fall 2007 Lecture 11, Slide 2The Inside of a 741 OpAmpDifferentialInput StageAdditionalGain StageOutput StageCurrent Sourcefor biasingBipolar versionhas small inputBias currentMOS OpAmpshave ~ 0 input currentGain is Sensitive to Operating Condition (e.g., Device, Temperature, Power supply voltage, etc.)Output devicesprovides largedrive current6.111 Fall 2007 Lecture 11, Slide 3Simple Model for an OpAmp+-i+ ~ 0i- ~ 0+-+-vidvoutvoutvidVCC = 10V-VCC = -10Vε = 100µ V-100µVReasonable approximation+-vid+-avid+-voutLinear Mode If -VCC < vout < VCC+-vid-VCC+-voutNegative Saturationvid < - ε-++-vid+-voutPositive Saturationvid > ε-++VCC-VCCVCCVery small input range for “open loop” configuration6.111 Fall 2007 Lecture 11, Slide 4The Power of (Negative) Feedbackinvoutv1R2R-+-+vid+-avid+-voutinvR2-+R1021=+++RvvRvvidoutidinavvoutid=!"#$%&++'=221111RRaRavRvoutin( )( )1112212>>!"++!= aifRRRRaaRvvinout Overall (closed loop) gain does not depend on open loop gain Trade gain for robustness Easier analysis approach: “virtual short circuit approach” v+ = v- = 0 if OpAmp is linear+-6.111 Fall 2007 Lecture 11, Slide 5Basic OpAmp CircuitsVoltage Follower (buffer)invoutv2R1RinRRRoutvv121+!+"Non-invertinginvoutv1invoutv2inv1R1R2R2R( )1212ininRRoutvvv −≈Differential Inputinoutvv≈invoutvRC∫∞−−≈tinRCoutd tvv1Integrator+-6.111 Fall 2007 Lecture 11, Slide 6OpAmp as a ComparatorAnalog Comparator: Is V+ > V- ? The Output is a DIGITAL signalLM311 uses asingle supplyvoltage6.111 Fall 2007 Lecture 11, Slide 72. Data Conversion: Noise• Quantization noise exists evenwith ideal A/D and D/Aconverters. SNR improves 6dBwith each additional bitA/D D/AdigitalcodeinvQuantizationnoise+!0001101104refV2refV43refVAnalog InputBinary OutputrefVA/D ConversioninvnoisevLSB0001101104refV2refV43refVBinary codeAnalog Output4refV2refV43refVrefVD/A Conversion6.111 Fall 2007 Lecture 11, Slide 8Non-idealities in Data ConversionBinary codeAnalogIdealOffseterrorOffset – a constant voltage offset that appearsat the output when the digital input is 0Binary codeAnalogIdealGainerrorGain error – deviation of slope from ideal valueof 1Binary codeAnalog IdealIntegralnonlinearityIntegral Nonlinearity – maximum deviation fromthe ideal analog output voltageDifferential nonlinearity – the largest incrementin analog output for a 1-bit changeBinary codeAnalog IdealNon-monoticity6.111 Fall 2007 Lecture 11, Slide 93. Digital to Analog• Common metrics:• Conversion rate – DC to ~500 MHz (video)• # bits – up to ~24• Voltage reference source (internal / external; stability)• Output drive (unipolar / bipolar / current) & settling time• Interface – parallel / serial• Power dissipation• Common applications:• Real world control (motors, lights)• Video signal generation• Audio / RF “direct digital synthesis”• Telecommunications (light modulation)• Scientific & Medical (ultrasound, …)6.111 Fall 2007 Lecture 11, Slide 10R-2R Ladder DAC Architecture Note that the driving point impedance (resistance) is the samefor each cell.• R-2R Ladder achieves large current division ratios with only tworesistor values-16.111 Fall 2007 Lecture 11, Slide 11Labkit: ADV7125 Triple Out Video DAC• Three 8-bit DACs• Single Supply Op.: 3.3 to 5V• Internal bandgap voltage ref• Output: 2-26 mA• 330 MSPS (million samples persecond)• Simple edge-triggered latchbased interface6.111 Fall 2007 Lecture 11, Slide 12Glitching and Thermometer D/A• Glitching is caused whenswitching times in a D/A are notsynchronized• Example: Output changes from011 to 100 – MSB switch isdelayed100011!outvt0TIRoutv( )210TTTIRvou t++−=II1T2T• Filtering reduces glitch butincreases the D/A settling time• One solution is a thermometercode D/A – requires 2N – 1switches but no ratioed currentsThermometerBinary11001111111001000000ThermometerBinary110011111110010000006.111 Fall 2007 Lecture 11, Slide 134. Analog to Digital• Common metrics:• Conversion rate – DC to ~100 MHz• # bits – up to ~20• Input range – unipolar / bipolar• Interface – parallel / serial• Type: successive approximation, sigma-delta, flash• Common applications:• Real world sensing (position, speed, force, temperature, …)• Video signal digitization• Audio / RF recording & receiving• Telecommunications (light demodulation)• Scientific & Medical6.111 Fall 2007 Lecture 11, Slide 14Successive-Approximation A/DExample: 3-bit A/D conversion, 2 LSB < Vin < 3 LSBVref0.5Vref0Vint = 0 t = 1 t = 2code = 100 code = 010 code = 011D/Aoutput01Comparator output010tt D/A converters are typically compact and easier to design. Why notA/D convert using a D/A converter and a comparator? DAC generates analog voltage which is compared to the input voltage If DAC voltage > input voltage then set that bit; otherwise, resetthat bit This type of ADC takes a fixed amount of time proportional to thebit lengthVincodeD/AComparatoroutC+ !6.111 Fall 2007 Lecture 11, Slide 15Successive-Approximation A/DSerial conversion takes a time equal to N (tD/A + tcomp)SuccessiveApproximationGeneratorControlDoneGo-+Sample/HoldD/AConvertervinNData6.111 Fall 2007 Lecture 11, Slide 16• Digitize differential signal:Sigma Delta ADCintegrator1-bit DAC++-Bit stream-+Analoginput1-bit ADCLPF DecimatorBit stream samplesREFV±REFINREFVVV <<!•Sigma Delta modulator runs at many times Nyquist frequency•Average of bit stream (1=VREF, 0=-VREF) gives voltage•Integrator is high-pass filter for noise, most of which is then removed by low-pass filter ⇒ excellent SNR (> 100dB)6.111 Fall 2007 Lecture 11, Slide 17Sigma Delta ADC• A simple ADC:RCVrefController(FPGA)VinRVinController(FPGA)C• Poor Man’s ADC:6.111 Fall 2007 Lecture 11, Slide 18Flash A/D Converter• Brute-force A/D conversion• Simultaneously compare theanalog value with everypossible reference value• Fastest method of A/Dconversion• Size scales exponentiallywith precision(requires 2N comparators)+−+−+−RRrefVinv0b1bTherm om eter to binaryComparatorsRR6.111 Fall 2007 Lecture 11, Slide 19High Performance Converters:Use Pipelining and
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