L10: Analog Building Blocks (OpAmps, A/D, D/A)Introduction to Operational AmplifiersThe Inside of a 741 OpAmpSimple Model for an OpAmpThe Power of (Negative) FeedbackBasic OpAmp CircuitsUse With Open LoopData Conversion: Quantization NoiseNon-idealities in Data ConversionR-2R Ladder DAC ArchitectureDAC (AD 558) SpecsChip Architecture and InterfaceSetting the Voltage RangeAnother Approach: Binary-Weighted DACGlitching and Thermometer D/ASuccessive-Approximation A/DSuccessive-Approximation A/DSuccessive-Approximation A/D (AD670)Single Write, Single Read Operation (see data sheet for other modes)Simple A/D Interface FSMExample A/D Verilog InterfaceExample A/D Verilog Interface (cont.)Example A/D Verilog Interface(cont.)SimulationFlash A/D ConverterAD 775 – Flash Data ConverterHigh Performance Converters: Use Pipelining and Parallelism!Summary of Analog BlocksL10: 6.111 Spring 2009 1Introductory Digital Systems LaboratoryL10: Analog Building Blocks(OpAmps, A/D, D/A)Acknowledgement: Dave WentzloffLecture Notes prepared by Professor Anantha ChadrakasanL10: 6.111 Spring 2009 2Introductory Digital Systems LaboratoryIntroduction to Operational Amplifiers Typically very high input resistance ~ 300KΩ High DC gain (~105) Output resistance ~75ΩDC ModelLM741 PinoutinoutVfaV⋅=)(a(f)f10Hz105-20dB/decade+10 to +15V-10 to -15Vidva⋅idvinRoutR+−outvL10: 6.111 Spring 2009 3Introductory Digital Systems LaboratoryThe Inside of a 741 OpAmpDifferentialInput StageAdditionalGain StageOutput StageCurrent Source for biasingBipolar versionhas small inputBias currentMOS OpAmpshave ~ 0 input currentGain is Sensitive to Operating Condition (e.g., Device, Temperature, Power supply voltage, etc.)Output devicesprovides largedrive currentL10: 6.111 Spring 2009 4Introductory Digital Systems LaboratorySimple Model for an OpAmp+-i+~ 0i-~ 0+-+-vidvoutvoutvidVCC= 10V-VCC= -10Vε = 100μV-100μVReasonable approximation+-vid+-avid+-voutLinear Mode If -VCC< vout < VCC+-vid-VCC+-voutNegative Saturationvid< - ε-++-vid+-voutPositive Saturationvid> ε-++VCC-VCCVCCSmall input range for “Open” loop ConfigurationL10: 6.111 Spring 2009 5Introductory Digital Systems LaboratoryThe Power of (Negative) Feedbackinvoutv1R2R-+-+vid+-avid+-voutinvR2-+R1021=+++RvvRvvidoutidinavvoutid=⎥⎦⎤⎢⎣⎡++−=221111RRaRavRvoutin()()1112212>>−≈++−= aifRRRRaaRvvinout Overall (closed loop) gain does not depend on open loop gain Trade gain for robustness Easier analysis approach: “virtual short circuit approach” v+= v-= 0 if OpAmp is linear+-L10: 6.111 Spring 2009 6Introductory Digital Systems LaboratoryBasic OpAmp Circuits+−Voltage Follower (buffer)Non-invertingDifferential Inputinvoutvinoutvv≈Integrator+-inoutvRRRv121+≈()1212ininRRoutvvv −≈dtvvtinRCout∫∞−−≈1L10: 6.111 Spring 2009 7Introductory Digital Systems LaboratoryUse With Open LoopAnalog Comparator:Is V+ > V- ?The Output is a DIGITAL signalLM311 is a single supplycomparatorL10: 6.111 Spring 2009 8Introductory Digital Systems LaboratoryData Conversion: Quantization Noise Quantization noise exists even with ideal A/D and D/A convertersinvnoisevLSBA/D D/AdigitalcodeinvQuantizationnoise+−00 01 101104refV2refV43refVBinary codeAnalog Output0001101104refV2refV43refVAnalog InputBinary OutputrefV4refV2refV43refVrefVA/D ConversionD/A ConversionL10: 6.111 Spring 2009 9Introductory Digital Systems LaboratoryNon-idealities in Data ConversionBinary codeAnalogIdealOffseterrorBinary codeAnalogIdealGainerrorOffset – a constant voltage offset that appears at the output when the digital input is 0Gain error – deviation of slope from ideal value of 1Binary codeAnalogIdealIntegralnonlinearityIntegral Nonlinearity – maximum deviation from the ideal analog output voltageDifferential nonlinearity – the largest increment in analog output for a 1-bit changeBinary codeAnalogIdealNon-monoticityL10: 6.111 Spring 2009 10Introductory Digital Systems LaboratoryR-2R Ladder DAC Architecture Note that the driving point impedance (resistance) is the same for each cell. R-2R Ladder achieves large current division ratios with only two resistor values-1L10: 6.111 Spring 2009 11Introductory Digital Systems LaboratoryDAC (AD 558) Specs 8-bit DAC Single Supply Operation: 5V to 15V Integrates required references (bandgap voltage reference) Uses a R-2R resistor ladder Settling time 1μs Programmable output range from0V to 2.56V or 0V to 10V Simple Latch based interfaceL10: 6.111 Spring 2009 12Introductory Digital Systems LaboratoryChip Architecture and InterfaceCECSLATCHD[7:0]Outputs are noisy when input bits settles, so it is best to have inputs stable before latching the input dataL10: 6.111 Spring 2009 13Introductory Digital Systems LaboratorySetting the Voltage RangeVery similar to anon-inverting ampStrap output fordifferent voltagerangesConvert data to Offset binaryL10: 6.111 Spring 2009 14Introductory Digital Systems LaboratoryAnother Approach: Binary-Weighted DAC Analog Devices AD9768 uses two banks of ratioed currents Additional current division performed by 750 Ω resistor between the two banks Switch binary-weighted currents MSB to LSB current ratio is 2NAD97683b2b1b0bRoutv( )0811412213bbbbIRvout+++−=+-I2II4I8Reference current sourceL10: 6.111 Spring 2009 15Introductory Digital Systems LaboratoryGlitching and Thermometer D/A Glitching is caused when switching times in a D/A are not synchronized Example: Output changes from 011 to 100 – MSB switch is delayed Filtering reduces glitch but increases the D/A settling time One solution is a thermometer code D/A – requires 2N –1 switches but no ratioed currents100011→outvtBinary Thermometer000000100110011111110TIRoutv()210TTTIRvout++−=II1T2TL10: 6.111 Spring 2009 16Introductory Digital Systems LaboratorySuccessive-Approximation A/DExample: 3-bit A/D conversion, 2 LSB < Vin< 3 LSB D/A converters are typically compact and easier to design. Why not A/D convert using a D/A converter and a comparator? D to A generates analog voltage which is compared to the input voltage If D to A voltage > input voltage then set that bit; otherwise, reset that bit This type of A to D takes a fixed amount of time proportional to the bit lengthVincodeD/AComparatoroutC+−L10: 6.111 Spring 2009 17Introductory Digital Systems LaboratorySuccessive-Approximation A/D Serial conversion takes a time equal to N(tD/A+
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