6.111 Lecture 8Perspective – Our Course AheadMemories of a Digital WorldMemory Classification & Metrics1. Static RAMs: Latch Based Memory1. Static RAMs: Latch Based MemoryMemory Array ArchitectureStatic RAM (SRAM) Cell (The 6-T Cell)2. Interacting with a Memory DeviceMCM6264C 8K x 8 Static RAMReading an Asynchronous SRAMAddress Controlled ReadsWriting to Asynchronous SRAMSample Memory Interface Logic3. Synchronous SRAM MemoriesZBT Eliminates the Wait StatePipelining Allows Faster CLK4. EPROMs and DRAMsDynamic RAM (DRAM) CellAsynchronous DRAM Operation5. Addressing with Memory MapsMemory Devices: Helpful KnowledgeSummary6.111 Fall 2005 Lecture 8, Slide 16.111 Lecture 8Today: Memories1.Static RAMs2.Interfacing: Bus & Protocol3.Synchronous Memories4.EPROMs and DRAMs5.Memory Mapped PeripheralsAcknowledgement: Nathan Ickes, Rex MinJ. Rabaey, A. Chandrakasan, B. Nikolic, “Digital Integrated Circuits: A Design Perspective” Prentice Hall, 2003 (Chapter 10)6.111 Fall 2005 Lecture 8, Slide 2Perspective – Our Course AheadDone with Lab 1. Where do we go from here?Digital Systems!Forward, Charge!ALUMEMFSMI/O FSMAnalogVideo1. Memories2. System Integration 3. Reconfigurable Logic4. Arithmetic Circuits5. Analog Building Blocks6. Video7. Power Dissipation8. Computer Architecture6.111 Fall 2005 Lecture 8, Slide 3Memories of a Digital WorldWhy need memories? State machines…Memories:- Flip Flips, Registers, FIFO (first-in-first-out)- Core memory!- Random Access (static/dynamic, read/write)- Slow / Non-volatile (hard drive/eeprom/eprom)- Content-addressable- Concept of a BUS and use of TRISTATE!www.psych.usyd.edu.auKey Design Metrics:1. Memory Density (number of bits/µm2) and Size2. Access Time (time to read or write) and Throughput 3. Power Dissipation6.111 Fall 2005 Lecture 8, Slide 4Memory Classification & MetricsRead-Write MemoryNon-VolatileRead-WriteMemoryRead-Only Memory (ROM)EPROME2PROMFLASHRandomAccessNon-RandomAccessSRAM DRAMMask-ProgrammedFIFOLIFOKey Design Metrics:1. Memory Density (number of bits/µm2) and Size2. Access Time (time to read or write) and Throughput 3. Power Dissipation6.111 Fall 2005 Lecture 8, Slide 51. Static RAMs: Latch Based MemorySet Reset Flip Flop Register MemorySQRQDQDCLKQ6.111 Fall 2005 Lecture 8, Slide 61. Static RAMs: Latch Based MemorySet Reset Flip Flop Register MemoryDQDQSQRQQDDQDQDQDQAddress Works fine for small memory blocks (e.g., small register files) Inefficient in area for large memories Densityis the key metric in large memory circuitsHow do we minimize cell size?6.111 Fall 2005 Lecture 8, Slide 7Memory Array ArchitectureInput-Output(M bits)2L-KBit LineWord LineStorage CellM.2KAmplify swing torail-to-rail amplitudeSelects appropriate word(i.e., multiplexer)Sense Amps/DriverColumn DecodeAK-1A0Row DecodeAKAK+1AL-12L-Krow byMx2Kcolumn cell arraySmall cells → small mosfets → small dV on bit line2LxM memory6.111 Fall 2005 Lecture 8, Slide 8Static RAM (SRAM) Cell (The 6-T Cell)WLBLVDDM5M6M4M1M2M3BLQQWLBLBLQQWrite: Set BL, BL to (0,VDD)or (VDD,0) then enable WL (= VDD)Read: Disconnect drivers from BL and BL, then enable WL (=VDD). Sense a small change in BL or BL State held by cross-coupled inverters (M1-M4) Retains state as long as power supply turned on Feedback must be overdriven to write into the memory2. Interacting with a Memory DeviceMemory Matrix……6.111 Fall 2005 Lecture 8, Slide 9• Address pins drive row and column decoders• Data pins are bidirectional:shared by reads and writes• Output Enable gates the chip’s tristate driver• Write Enable sets the memory’s read/write mode• Chip Enable/Chip Selectacts as a “master switch”Data PinsReadLogicWriteLogicRow DecoderAddress PinsSense Amps/DriversColumn DecoderWrite enableChip EnableOutput EnableTri-state DriverinoutenableIf enable=0out = ZIf enable =1out = inWrite enableConcept of “Data Bus”MCM6264C 8K x 8 Static RAM6.111 Fall 2005 Lecture 8, Slide 10DQ[7:0]Memory matrix256 rows32 ColumnRow DecoderColumn DecoderSense Amps/Drivers……A2A3A4A5A7A8A9A11A0A1A6A10A12E1E2WGMCM6264CAddressDataDQ[7:0]138Chip Enables E1E2Write Enable WEOutput Enable OEOn the outside:On the inside:Same (bidirectional) data bus used for reading and writingChip Enables (E1 and E2)E1 must be low and E2 must be high to enable the chipWrite Enable (WE)When low (and chip enabled), values on data bus are written to location selected by address busOutput Enable (OE or G)When low (and chip is enabled), data bus is driven with value of selected memory locationPinout6.111 Fall 2005 Lecture 8, Slide 11Reading an Asynchronous SRAMBus tristate timeAddress ValidData ValidBus enable timeAddressAccess time (from address valid)E1OEAccess time (from enable low)(Tristate)Data• Read cycle begins when all enable signals (E1, E2, OE) are active • Data is valid after read access time– Access time is indicated by full part number: MCM6264CP-12 Æ12ns• Data bus is tristated shortly after OE or E1 goes highE2 assumed high (enabled), W =1 (read mode)6.111 Fall 2005 Lecture 8, Slide 12Address Controlled ReadsBus tristate timeAccess time (from address valid)AddressE1OEBus enable timeDataAddress 3Address 2Address 1Data 2Data 3Data 1Contamination timeE2 assumed high (enabled), WE =1 (read mode)• Can perform multiple reads without disabling chip• Data bus follows address bus, after some delay6.111 Fall 2005 Lecture 8, Slide 13Writing to Asynchronous SRAMAddress ValidAddressAddress setup time Address hold timeE1WE• Data latched when WE or E1 goes high (or E2 goes low)– Data must be stable at this time– Address must be stable before WE goes low• Write waveforms are more important than read waveforms– Glitches to address can cause writes to random addresses!DataWrite pulse widthData setup timeData ValidE2 and OE are held highData hold time6.111 Fall 2005 Lecture 8, Slide 14Sample Memory Interface LogicClock/E1OEWEAddressDataData for writeAddress for write Address for readData readWrite occurs here, when E1 goes highData can be latched hereDrive data bus only when clock is low– Ensures address are stable for writes– Prevents bus contention– Minimum clock period is twice memory access timeWrite cycle Read cycleFSMClockDQAddressRead dataWrite dataControl(write, read, reset)Data[7:0]Address[12:0]WGE1SRAME2VCCext_chip_enableext_write_enableext_output_enableext_addressext_dataQDQDint_dataFPGA3. Synchronous SRAM Memories• Clocking provides input synchronization and encourages more
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