Welcome to 6.111! • Introductions, course mechanics • Course overview • Digital signaling • Combinational logic • 4 Handouts: calendar, slides, LP #1, info form 6.111 Fall 2009 1 Lecture 1 Introductions 6.111 Fall 2009 Lecture 1 2 Chris Terman Gim Hom 6.111 Labkit 6M-gate FPGA + audio + video + memories + … !"#$%&'()*%+,-%.-/01%20-%$34401%Adam Lerer Course Website: http://web.mit.edu/6.111/www/f2009 6.111 Fall 2009 Lecture 1 3 • One stop shopping for all 6.111 information • Handouts • Labs • On-line submissions • Policies • … • Please read “Course info” to get oriented%Assignments 6.111 Fall 2009 Lecture 1 4 Lecture Problems (20%) Labs (30%) CI-M Paper (10%) Final Project (40%) A large number of students do "A" level work and are, indeed, rewarded with a grade of "A". The corollary to this is that, since average performance levels are so high, punting any part of the subject can lead to a disappointing grade.Labs: learning the ropes • Lab 1 – Experiment with gates, design & implement some logic – Learn about lab equipment in the Digital Lab (38-600): oscilloscopes and logic analyzers • Lab 2 – Introduction to Verilog & the labkit • Lab 3 – Design and implement a Finite State Machine (FSM) – Use Verilog to program an FPGA – Report and its revision will be evaluated for CI-M • Lab 4 – Design a complicated system with multiple FSMs (Major/Minor FSM) – Implementing arithmetic units, using on-chip memories • Lab 5 – Video circuits: a simple Pong game 6.111 Fall 2009 Lecture 1 5 Final Project • Done in groups of two (or sometimes three) • Open-ended • You and the staff negotiate a project proposal – Must emphasize digital concepts, but inclusion of analog interfaces (e.g., data converters, sensors or motors) common and often desirable – Proposal Conference, several Design Reviews • Design presentation to class • Staff will provide help with project definition and scope, design, debugging, and testing • It is extremely difficult for a student to receive an A without completing the final project. Sorry, but we don’t give incompletes. 6.111 Fall 2009 Lecture 1 6 6.111 Topics 6.111 Fall 2009 Lecture 1 7 Digital Building Blocks & Architecture Design Methodologies & Tools Implementation Technologies • Combinational logic • Sequential Logic • Memories • Performance issues • … • FPGAs • Flash, ZBT ram • AC97, TripleDAC • … • Design metrics • HDL: Verilog • Simulation tools • Synthesis, Place & Route • … The trouble with analog signaling 6.111 Fall 2009 Lecture 1 8 The real world is full of continuous-time continuous-value (aka “analog”) signals created by physical processes: sound vibrations, light fields, voltages and currents, phase and amplitudes, … But if we build processing elements to manipulate these signals we must use non-ideal components in real-world environments, so some amount of error (aka “noise”) is introduced. The error comes from component tolerances, electrical phenomenon (e.g., IR and LdI/dt effects), transmission losses, thermal noise, etc. Facts of life that can’t be avoided… And the more analog processing we do, the worse it gets: signaling errors accumulate in analog systems since we can’t tell from looking at signal which wiggles were there to begin with and which got added during processing. Processing ElementSolution: go digital! Continuous values Continuous time Discrete values Discrete time 6.111 Fall 2009 Lecture 1 9 So we can detect small changes and restore original values So we don’t look while it’s changing The Digital Abstraction 6.111 Fall 2009 Lecture 1 10 Real Analog World “Ideal” Digital World Volts or Electrons or Ergs or Gallons Bits 0/1 Noise Manufacturing Variations Keep in mind that the world is not digital, we would simply like to engineer it to behave that way. Furthermore, we must use real physical phenomena to implement digital designs! Noise and inaccuracy are inevitable; we can’t reliably engineer perfect components – we must design our system to tolerate some amount of error if it is to process information reliably. Digital Signaling: sending To ensure we can distinguish signal from noise, we’ll encode information using a fixed set of discrete values called symbols. Given a bound N on the size of possible errors, if the analog representations for the symbols are chosen to be at least 2N apart, we should be able to detect and eliminate errors of up to ±N. -N +N “C” -N +N “B” -N +N “A” -N +N “D” -N +N “E” Since we will use non-ideal components in the sender, we allow each transmitted symbol to be represented by a (small) range of analog values. -N +N “C” -N +N “D” -N +N “E” -N +N “B” -N +N “A” 6.111 Fall 2009 Lecture 1 11 IDEAL SEND Digital Signaling: receiving Since the channel/wire is imperfect and we will use non-ideal components in the receiver, we require the receiver to accept a (larger) range of analog values for each symbol. -N +N “C” -N +N “B” -N +N “A” -N +N “D” -N +N “E” To avoid hard-to-make decisions at the boundaries between symbol representations, insert a “forbidden zone” between symbols so that some ranges of received values are not required to be mapped to a specific symbol. forbidden zones 6.111 Fall 2009 Lecture 1 12 RCVDigital processing elements 6.111 Fall 2009 Lecture 1 13 Digital processing elements restore noisy input values to legal output values – signaling errors don’t accumulate in digital systems. So the number of processing elements isn’t limited by noise problems! The “trick” is that we’ve defined our signaling convention so that we can tell from looking at a signal which wiggles were there to begin with and which got added during processing. Processing Element -N +N “D” -N +N “D” IN OUT Using voltages to encode binary values OUTPUTS: INPUTS: Forbidden Zone volts 0 VDD VOL 0OUT 1OUT VOH volts 0 VDD VIL 0IN 1IN VIH VOL VOH Noise Margins We’ll keep things simple by designing our processing elements to use voltages to encode binary values (0 or 1). To ensure robust operation we’d like to make the noise margins as large as possible. 6.111 Fall 2009 Lecture 1 14 Digital Signaling Specification
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