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MIT 6 111 - Lecture Slides

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Potpourri • Serial communication links • FFTs • FPGAs @ home • Project Schedule 6.111 Fall 2009 1 Lecture 14 Lab #5 due tonight, project abstract next Monday !"#$%&'(&)*+&,-.!&,/0!12/&3$4#$)"5%&627!789&6:2;.<:=&!*>?&@@AB&CDEFGHDFF&ECG@HH&Serial Communications • Sending information one bit at a time vs. many bits in parallel – Serial: good for long distance (save on cable, pin and connector cost, easy synchronization). Requires “serializer” at sender, “deserializer” at receiver – Parallel: issues with clock skew, crosstalk, interconnect density, pin count. Used to dominate for short-distances (eg, between chips). – BUT modern preference is for parallel, but independent serial links (eg, PCI-Express) as a hedge against link failures. • A zillion standards – Asynchronous (no explicit clock) vs. Synchronous (CLK line in addition to DATA line). – Recent trend to reduce signaling voltages: save power, reduce transition times – Control/low-bandwidth Interfaces: SPI, I2C, 1-Wire, PS/2, AC97 – Networking: RS232, Ethernet, T1, Sonet – Computer Peripherals: USB, FireWire, Fiber Channel, Infiniband, SATA, Serial Attached SCSI 6.111 Fall 2009 2 Lecture 14 RS232 (aka “serial port”) • Labkit: simple bidirectional data connection with computer. • Characteristics – Large voltages => special interface chips (1/mark: -12V to -3V, 0/space: 3V to 12V) – Separate xmit and rcv wires: full duplex – Slow transmission rates (1 bit time = 1 baud); most interfaces support standardized baud rates: 1200, 2400, 4800, 9600, 19.2K, 38.4K, 57.6K, 115.2K – Format • Wire is held at 1/mark when idle • Start bit (1 bit of “0” at start of transmission) • Data bits (LSB first, can be 5 to 8 bits of data) • Parity bit (none, even, odd) • Stop bits (1, 1.5 or 2 bits of 1/mark at end of symbol) • Most common 8-N-1: eight data bits, no parity, one stop bit 6.111 Fall 2009 3 Lecture 14 RS232 interface • Transmit: easy, just build FSM to generate desired waveform with correct bit timing • Receive: – Want to sample value in middle of each bit time – Oversample, eg, at 16x baud rate – Look for 1->0 transition at beginning of start bit – Count to 8 to sample start bit, then repeatedly count to 16 to sample other bits – Check format (start, data, parity, stop) before accepting data. Figure from http://www.arcelect.com/rs232.htm 6.111 Fall 2009 4 Lecture 14SPI (Serial Peripheral Interface) • Simple, 3-wire interface + devices selects – SCLK generated by master (1-70MHz). Assert data on one edge, sample data on the other. Default state of SCLK and assignment of edges is often programmable. – Master Out Slave In (MOSI) data shifted out of master register into slave register – Master In Slave Out (MISO) data shifted out of slave register and into master register – Selects (usually active low) determine which device is active. Assertion often triggers an action in the slave, so master waits some predetermined time then shifts data. Figures from Wikipedia 6.111 Fall 2009 5 Lecture 14 I2C (Inter-Integrated Circuit) • 2 open-drain wires (SCL = clock, SDA = data) • Multiple-master, each transmission addresses a particular device, many devices have many different sub-addresses (internal registers) • Format (all addresses/data send MSB first): – Sender: Start [S] bit (SDA! while SCL high) – Sender: One or more 8-bit data packets, each followed by 1-bit ACK • Data changed when SCL low, sampled at SCL" • Receiver: Active-low ACK generated after each data packet – Sender: Stop [P] bit (SDA" while SCL high) • SCL and SDA have pullup resistors, senders only drive low, go high-impedance to let pullups make line high (so multiple drivers okay!) – Receiver can hold SCL low to stretch clock timing, sender must wait until SCL goes high before moving to next bit. – Multiple senders can contend using SDA for arbitration Figures from Wikipedia 6.111 Fall 2009 6 Lecture 14 PS/2 Keyboard/Mouse Interface • 2-wire interface (CLK, DATA), bidirectional transmission of serial data at 10-16kHz • Format – Device generates CLK, but host can request-to-send by holding CLK low for 100us – DATA and CLK idle at “1”, CLK starts when there’s a transmission. DATA changes on CLK", sampled on CLK! – 11-bit packets: one start bit of “0”, 8 data bits (LSB first), odd parity bit, one stop bit of “1”. – Keyboards send scan codes (not ASCII!) for each press, 8’hF0 followed by scan code for each release – Mice send button status, Δx and Δy of movement since last transmission Figures from digilentinc.com 6.111 Fall 2009 7 Lecture 14 USB (Universal Serial Bus) • 2-wire (D+,D-) for high-speed, bidirectional polled transmission between master and addressable endpoints in multiple devices. Full speed (12Mbps) and High speed (480Mbps) data rates. • Multi-level tiered-star topology (127 devices, including hubs) • FTDI UM245R USB-to-FIFO module for bidirectional data transfer using a handshake protocol, also asynchronous “bit-bang” mode with selectable baud rates. – 24-pin DIP module, wire to user pins – Drivers for Windows workstations in lab Figures from ftdi.com 6.111 Fall 2009 8 Lecture 14Audio Feature Extraction • Most features are best recognized in the frequency domain • Use Discrete Fourier Transform – Algorithm used: Fast Fourier Transform (FFT) – Input: N data values acquired at sample frequency ωS • Nyquist rate is ωS/2 – Output: N complex values representing DFT coefficients in the frequency range −ωS/2 to +ωS/2. • Each value covers a frequency range of ωS/N • Indices (0,(N/2)-1) are for frequencies i*(ωS/N) • Indices (N/2,N-1) are for frequencies −ωS/2 + (i – N/2)*(ωS/N) – If N is even, output is symmetric, so we can calculate magnitude using only positive frequencies. Magnitude ! * constant factors. • Example – Audio data from AC97 sampled at 8kHz – 2048 data points => 2048-point FFT – 2048 complex results, each result covers 8k/2048 = 4Hz range ! r2+ i26.111 Fall 2009 9 Lecture 14 Iterative SQRT module // takes integer square root iteratively module sqrt #(parameter NBITS = 8, // max 32 MBITS


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MIT 6 111 - Lecture Slides

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