6.111 FINAL PROJECT MUSIC VISUALIZER Abstract This paper discusses the creation of a music visualization system, from planning to design, implementation, testing, and debugging. Working in a team of three, we each took control of a part of our project, and all worked to put the parts together to form the visualization system, which used the Verilog hardware description language. Our target was to create a system which could take in audio from a headphone jack and output a visualization of the audio, similar to ones seen in Winamp or Windows Media Player, to a television through an RCA connector. Building the visualizer as a team was a very valuable learning experience, illuminating many aspects of hardware design and planning. Table of Contents Abstract ............................................................................................................................... 1 Table of Contents................................................................................................................ 2 Table of Figures .................................................................................................................. 3 Introduction......................................................................................................................... 4 Description.......................................................................................................................... 4 The Analog Audio Processing Layer (Bradley Edwards)................................................ 5 Audio (Lab 3) Module ................................................................................................ 5 Recorder Module ........................................................................................................ 6 Bucketizer Module...................................................................................................... 7 Multiplier Module....................................................................................................... 7 The Visualizer Layer (Stephen Oney) ............................................................................. 8 Information Distribution Module................................................................................ 8 Address Module .......................................................................................................... 9 Visualization Selection Module.................................................................................. 9 The “Doer” Module .................................................................................................... 9 The Bar Visualization ................................................................................................. 9 The Diagonal Bar Visualization.................................................................................. 9 The “Radial” Visualization....................................................................................... 10 The Intersecting Circles Visualization...................................................................... 10 The Visualizer Module ............................................................................................. 11 The Video Output Layer (Aston Motes)........................................................................ 11 Dual-Port RAM Module ........................................................................................... 11 RGB to YCrCb Module ............................................................................................ 11 Signal Generator/DAC Control................................................................................. 12 Horizontal and Vertical Position to RAM Address Module..................................... 14 Equalizer Module...................................................................................................... 14 PS/2 ASCII Input Module......................................................................................... 15 Bucket Generator Module......................................................................................... 15 Testing and Debugging ..................................................................................................... 15 Conclusion ........................................................................................................................ 17 Appendix – Source Code to Selected Modules................................................................. 19 Adv7194init.v ................................................................................................................ 19 Avtest.v .......................................................................................................................... 27 Equalizer.v ..................................................................................................................... 38 Gen_buckets.v................................................................................................................ 43 Ps2_kbd.v.......................................................................................................................... 45 Video.v........................................................................................................................... 49 Visualizer.v .................................................................................................................... 56 Audio (Lab 3.v) – included in Avtest.v ......................................................................... 70 Recorder. v..................................................................................................................... 70 Bucketizer. v .................................................................................................................. 74 Multiplier.v .................................................................................................................... 76 Timing Diagram for 1024-pt FFT.................................................................................. 77Table of Figures Figure 1 - The Audio Processing Layer.............................................................................. 5 Figure 2 - Schematic
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