Appendix Top Level Labkit Code (developed by Nathan Ickes and modified for project) /////////////////////////////////////////////////////////////////////////////// // // 6.111 FPGA Labkit -- Audio/Video Test // // For Labkit Revision 004 // // Created: November 3, 2004 // Author: Nathan Ickes // /////////////////////////////////////////////////////////////////////////////// module labkit (beep, audio_reset_b, ac97_sdata_out, ac97_sdata_in, ac97_synch, ac97_bit_clock, vga_out_red, vga_out_green, vga_out_blue, vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync, vga_out_vsync, tv_out_ycrcb, tv_out_reset_b, tv_out_clock, tv_out_i2c_clock, tv_out_i2c_data, tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b, tv_out_subcar_reset, tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, tv_in_aef, tv_in_hff, tv_in_aff, tv_in_i2c_clock, tv_in_i2c_data, tv_in_fifo_read, tv_in_fifo_clock, tv_in_iso, tv_in_reset_b, tv_in_clock, ram0_data, ram0_address, ram0_adv_ld, ram0_clk, ram0_cen_b, ram0_ce_b, ram0_oe_b, ram0_we_b, ram0_bwe_b, ram1_data, ram1_address, ram1_adv_ld, ram1_clk, ram1_cen_b, ram1_ce_b, ram1_oe_b, ram1_we_b, ram1_bwe_b, clock_feedback_out, clock_feedback_in, flash_data, flash_address, flash_ce_b, flash_oe_b, flash_we_b, flash_reset_b, flash_sts, flash_byte_b, rs232_txd, rs232_rxd, rs232_rts, rs232_cts, mouse_clock, mouse_data, keyboard_clock, keyboard_data, clock_27mhz, clock1, clock2, disp_blank, disp_data_out, disp_clock, disp_rs, disp_ce_b, disp_reset_b, disp_data_in, button0, button1, button2, button3, button_enter, button_right, button_left, button_down, button_up, switch, led, user1, user2, user3, user4, daughtercard,systemace_data, systemace_address, systemace_ce_b, systemace_we_b, systemace_oe_b, systemace_irq, systemace_mpbrdy, analyzer1_data, analyzer1_clock, analyzer2_data, analyzer2_clock, analyzer3_data, analyzer3_clock, analyzer4_data, analyzer4_clock); output beep, audio_reset_b, ac97_synch, ac97_sdata_out; input ac97_bit_clock, ac97_sdata_in; output [7:0] vga_out_red, vga_out_green, vga_out_blue; output vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync, vga_out_vsync; output [9:0] tv_out_ycrcb; output tv_out_reset_b, tv_out_clock, tv_out_i2c_clock, tv_out_i2c_data, tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b, tv_out_subcar_reset; input [19:0] tv_in_ycrcb; input tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, tv_in_aef, tv_in_hff, tv_in_aff; output tv_in_i2c_clock, tv_in_i2c_data, tv_in_fifo_read, tv_in_fifo_clock, tv_in_iso, tv_in_reset_b, tv_in_clock; inout [35:0] ram0_data; output [20:0] ram0_address; output ram0_adv_ld, ram0_clk, ram0_cen_b, ram0_ce_b, ram0_oe_b, ram0_we_b; output [3:0] ram0_bwe_b; inout [35:0] ram1_data; output [20:0] ram1_address; output ram1_adv_ld, ram1_clk, ram1_cen_b, ram1_ce_b, ram1_oe_b, ram1_we_b; output [3:0] ram1_bwe_b; input clock_feedback_in; output clock_feedback_out; inout [15:0] flash_data; output [24:0] flash_address; output flash_ce_b, flash_oe_b, flash_we_b, flash_reset_b, flash_byte_b; input flash_sts; output rs232_txd, rs232_rts; input rs232_rxd, rs232_cts; input mouse_clock, mouse_data, keyboard_clock, keyboard_data; input clock_27mhz, clock1, clock2; output disp_blank, disp_clock, disp_rs, disp_ce_b, disp_reset_b; output disp_data_out; input disp_data_in; input button0, button1, button2, button3, button_enter, button_right, button_left, button_down, button_up; input [7:0] switch; output [7:0] led;inout [31:0] user1, user2, user3, user4; inout [43:0] daughtercard; inout [15:0] systemace_data; output [6:0] systemace_address; output systemace_ce_b, systemace_we_b, systemace_oe_b; input systemace_irq, systemace_mpbrdy; output [15:0] analyzer1_data, analyzer2_data, analyzer3_data, analyzer4_data; output analyzer1_clock, analyzer2_clock, analyzer3_clock, analyzer4_clock; //////////////////////////////////////////////////////////////////////////// // // Reset Generation // // A shift register primitive is used to generate an active-high reset // signal that remains high for 16 clock cycles after configuration finishes // and the FPGA's internal clocks begin toggling. // //////////////////////////////////////////////////////////////////////////// wire reset; SRL16 reset_sr (.D(1'b0), .CLK(clock_27mhz), .Q(reset), .A0(1'b1), .A1(1'b1), .A2(1'b1), .A3(1'b1)); defparam reset_sr.INIT = 16'hFFFF; //////////////////////////////////////////////////////////////////////////// // // Audio Input and Output // //////////////////////////////////////////////////////////////////////////// wire [3:0] vol; wire [39:0] vdisp; wire volume_up, volume_down; //////////******debugging wires wire [19:0] left_in_data; wire fftdone, rdy, busy, ovflo; wire [9:0] xn_index, xk_index; wire [15:0] xk_re, xk_im, xn_re, xn_im; wire start; wire [10:0] waddress; wire fwd_inv; wire resetout, n_fft_we, fwd_inv_we; wire [4:0] value;wire [9:0] scale_sch, max_index; wire [4:0] n_fft; wire rom_enable; audio audio1 (reset, clock_27mhz, audio_reset_b, ac97_sdata_out, ac97_sdata_in, ac97_synch, ac97_bit_clock, switch[1:0], {vol, 1'b0}, switch[2], left_in_data, fftdone, rdy, busy, ovflo, xn_index, xk_index, xk_re, xk_im, xn_re, xn_im, n_fft, n_fft_we, fwd_inv, fwd_inv_we, scale_sch, scale_sch_we, start, ce, waddress, resetout, value, max_index, rom_enable); beeper beep1 (reset, clock_27mhz, beep, ~button_enter); debounce vol_up (reset, clock_27mhz, button_up, volume_up); debounce vol_down (reset, clock_27mhz, button_down, volume_down); volume vol1 (reset, clock_27mhz, volume_up, volume_down, vol, vdisp); //////////////////////////////////////////////////////////////////////////// // // Default I/O Assignments // //////////////////////////////////////////////////////////////////////////// // SRAMs assign ram0_data = 36'hZ; assign
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