6.111 Fall 2005 Lecture 2, Slide 1Example device: A Buffer0011Static Discipline requires that we avoid the shaded regions aka“forbidden zones”), which correspond to validinputs but invalidoutputs. Net result: combinational devices must have GAIN > 1and be NONLINEAR.Voltage Transfer Characteristic(VTC):Plot of Voutvs. Vinwhere eachmeasurement is taken after anytransients have died out.VoutVinVOLVOHVILVIHNote: VTC does not tell you anything about how fast a device is—it measures static behavior not dynamic behaviorVTC for inverting gates6.111 Fall 2005 Lecture 2, Slide 2Due to unavoidable delays…Propagation delay (tPD):An UPPER BOUND on the delay from valid inputsto valid outputs.GOAL:minimizepropagationdelay!ISSUE:keep Capacitanceslow andtransistorsfastVOUT< tPD< tPDVINVOLVOHVILVIHtime constantτ = RPD•CLtime constantτ = RPU•CL6.111 Fall 2005 Lecture 2, Slide 3Contamination Delayan optional, additional timing specINVALID inputs take time to propagate, too...CONTAMINATION DELAY, tCDA LOWER BOUND on the delay from any invalid input to an invalid outputVOUT> tCD> tCDVINVOLVOHVILVIHDo we really need tCD?Usually not… it’ll be important when we design circuits with registers (coming soon!)If tCDis not specified, safe to assume it’s 0.Do we really need tCD?Usually not… it’ll be important when we design circuits with registers (coming soon!)If tCDis not specified, safe to assume it’s 0.6.111 Fall 2005 Lecture 2, Slide 4The Combinational ContractABA B0 11 0tPDpropagation delaytCDcontamination delayABMust be ___________Must be ___________Note:1. No Promises during 2. Default (conservative) spec: tCD= 0< tPD> tCD6.111 Fall 2005 Lecture 2, Slide 5Example: Timing AnalysisIf NAND gates have a tPD= 4nS and tCD= 1nSBCAYtPD= _______ nStCD= _______ nS122tPDis the maximumcumulative propagation delay over all paths from inputs to outputstCDis the minimumcumulative contamination delay over all paths from inputs to outputs6.111 Fall 2005 Lecture 2, Slide 6The “perfect” logic family• Good noise margins (want a “step” VTC)• Implement useful selection of (binary) logic– INVERTER, NAND, NOR with modest fan-in (4? Inputs)– More complex logic in a single step? (minimize delay)• Small physical size– Shorter signal transmission distances (faster)– Cost proportional to size (cheaper)• Inexpensive to manufacture– “print” technology (lithographic masks, deposition, etching)– Large-scale integration• Minimal power consumption– Portable– Massive processing without meltdown6.111 Fall 2005 Lecture 2, Slide 7Transitor-transitor Logic (TTL)74LS04(courtesy TI)Q1Q2Q3+-vBE+-vCEECBRTLDTLTTLTTL w/ totem pole outputs(“on” threshold = 2 diode drops)NPN BJTICE= βIBE6.111 Fall 2005 Lecture 2, Slide 8TTL Signaling• Typical TTL signaling spec– IOL = 16mA, IOH= -0.4mA (VOL=0.4V, VOH=2.7V, VCC=5V)– IIL= -1.6mA, IIH= 0.04mA (VIL=0.8V, VIH=2.0V)– Switching threshold = 1.3V• Each input requires current flow (IIL,IIH) and each output can only source/sink a certain amount of current (IOL,IOH), soMax number of inputs that can be driven by a single output is min(-IIL/IOL,-IIH/IOH) ≈ 10.• Current-based logic → power dissipation even in steady state, limitations on fanout6.111 Fall 2005 Lecture 2, Slide 9Complementary MOS LogicVinVoutDS = 0VGIPDIPDVOUTVIN = 5vIPDvs VOUTfor PULLDOWNVIN = 4vVIN = 3vVIN = 2vVIN = 1vS = VDDGDIPUIPUVOUTIPUvs VOUTfor PULLUPVIN = 0vVIN = 1vVIN = 2vVIN = 3vVIN = 4vP-Channel MOSFETN-Channel MOSFETMOSFET:IDS= f(VGS,VDS)6.111 Fall 2005 Lecture 2, Slide 10VOLVILVIHVOHCMOS Inverter VTCVinVoutVoutVin= 0.5VIpuIpdVoutVin= 1.5VIpuIpdWhen both fets are saturated, small changes in Vinproduce large changes in VoutVin= 2.5VVoutIpuIpdVin= 4.5VVoutIpuIpdVin= 3.5VVoutIpuIpdIpuIpdSteady state reached when Voutreaches value where Ipu= Ipd.6.111 Fall 2005 Lecture 2, Slide 11CMOS Signaling• Typical CMOS signaling specifications:– VOL≈ 0,VOH≈ VDD (VDDis the power supply voltage)– VIL≈ just under VDD/2,VIH≈ just over VDD/2– Great noise margins! ~VDD/2• Inputs electrically isolated from outputs:– An output can drive many, many inputs without violating signaling spec (but transitions will get slower)• In the steady state, signals are either “0” or “1”– When VOUT= 0V, IPD= 0 (and IPU= 0 since pullup is off)– When VOUT= VDD, IPU= 0 (and IPD= 0 since pulldown is off)– No power dissipated in steady state!– Power dissipated only when signals change (ie, power proportional to operating frequency).6.111 Fall 2005 Lecture 2, Slide 12Multiple interconnect layersMetal 2M1/M2 viaMetal 1PolysiliconDiffusionMosfet (under polysilicon gate)IBM photomicrograph (SiO2has been removed!)6.111 Fall 2005 Lecture 2, Slide 13Big Issue 1: Wires• Today (i.e., 100nm): τRC≈ 50ps/mmImplies > 1 ns to traverse a 20mm x 20mm chipThis is a long time in a 2GHz processorVINRVoutVINC6.111 Fall 2005 Lecture 2, Slide 14Big Issue 2: Power• Energy dissipated = C VDD2 per gatePower consumed = f n C VDD2per chipwhere f = frequency of charge/dischargen = number of gates /chipVINVDDCVOUTVINmoves from L to H to LVOUTmoves from H to L to HC discharges and then recharges6.111 Fall 2005 Lecture 2, Slide 15Unfortunately…• Modern chips (UltraSparc III, Power4, Itanium 2) dissipate from 80W to 150W with a Vdd ≈ 1.2V(Power supply current is ≈ 100 Amps)Hey: could wesomehow recyclethe charge?32 Amps (@220v)•Worse yet…– Little room left to reduce Vdd– nC and f continue to grow• Cooling challenge is like making the filament of a 100W incandescent lamp cool to the touch!MIT Computation Centerand PizzeriaI’ve got the solution!6.111 Fall 2005 Lecture 2, Slide 16CMOS Gate Recipe: Think Switchespullup: make this connection when VINnear 0 so that VOUT= VDDpulldown: make this connection shen VINnear VDDso that VOUT= 0VDDVINVOUTVIN≤ VILVOUT≥ VOHLHVIN≥ VIHHLVOUT≤ VOLOne power supply →Two voltages (VDD, GND) →Binary signalingOne power supply →Two voltages (VDD, GND) →Binary signaling6.111 Fall 2005 Lecture 2, Slide 17Beyond Inverters:Complementary pullups and pulldownsWe want complementarypullup and pulldownlogic, i.e., the pulldown should be “on” when the pullup is “off” and vice versa.pullup pulldown F(A1,…,An)on off driven “1”off on driven “0”on on driven “X”off off no connectionNow you know what the “C”in CMOS stands for!Since there’s plenty of capacitance on the output node,
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