Massachusetts Institute of TechnologyDepartment of Electrical Engineering and Computer Science6.111 – Introductory Digital Systems LaboratoryProblem Set 3Problem Set Issued: March 3, 2006Problem Set Due: March 15, 2006Problem 1: Critical Path Timing AnalysisThe Figure below is the 16-bit Carry-Bypass Adder from Lecture 8 (see notes for a clear blockdiagram).Figure 1: Carry-bypass adderAssume the following delay for each gate:Producing Pi, Gi from Ai, Bi: 1 unitPi, Gi, Ci to Co or Sum for a FA: 1 unit2:1 mux delay: 1 delay unitBP: It takes 1 delay unit to generate BP from the propagate signals.What is the worst case propagation delay for the 16-bit adder?Problem 2: Twos Complement MultiplierA 4x4 Twos Complement Multiplier was presented in lecture. In this problem, you will design acombinational 8x8 Twos Complement Multiplier in Verilog, and validate your design using atestbench.Your multiplier should take as input the two’s complement numbers X [7:0] and Y [7:0], and giveas output a twos complement number Z. How many bits will Z have?a) Code the multiplier you designed above in Verilog and validate it using a testbench.b) Implement a second twos complement multiplier in Verilog, only this time use the signedmodifier and the * operator.For this problem, turn in Verilog code for your multiplier and testbench. We also ask that yousubmit a screen capture of your simulation.Problem 3: Generating Block RAMsa) Generate a 16x16 Block RAM module using CoreGen. b) Design a module “test_mem” that writes data into one of the locations (pick any address)and then reads the data from the same location. Verify that the data were written correctly.Problem 4: Introduction to VideoIn this problem you will build part of a video controller, and use ModelSim to verify its correctoperation. To get you started, a brief overview of VGA video generation follows. For additionalguidance, refer to the URL:http://www-mtl.mit.edu/Courses/6.111/lab kit/vga.shtmlTo maintain a stable image on a monitor, a video controller must repeatedly output the entirecontents of the screen, one pixel at a time, at the desired screen refresh rate (usually 60 Hz orabove). Usually this is accomplished by filling a memory with the desired screen image, andreading from the memory in a cyclic fashion.The screen is redrawn one pixel row at a time, from left to right. Rows are drawn from top tobottom to form a complete image. To specify how quickly the image should be redrawn, displaysrequire horizontal and vertical sync signals that pulse once per row and once per screen redraw,respectively. Thus, on the 640x480 display you will be using, the horizontal sync pulses(approximately) 640 times per vertical sync, and the vertical sync pulses (approximately) 75times per second to specify a screen refresh rate of 75 Hz. The horizontal and vertical sync areactive low; their default state is a 1, and their periodic pulse is a 0.In this video mode, one pixel is drawn every 31.75 ns. This is another way of saying that ourpixel clock is running at 31.5 MHz. You can generate this clock signal by instantiating a XilinxDigital Clock Manager (DCM). Documentation on the Xilinx DCM can be found at this address:http://tinyurl.com/h74gk. The FPGA you are using has several DCM’s and these can be used tocreate signals with frequencies that are multiples of a reference signal. You can instantiate a DCMin your top level module with the following lines of code:DCM pixel_clock_dcm (.CLKIN(clock_27mhz),.CLKFX(pixel_clock)); // synthesis attribute CLKFX_MULTIPLY of pixel_clock_dcm is 7 // synthesis attribute CLKFX_DIVIDE of pixel_clock_dcm is 6 // synthesis attribute CLKIN_PERIOD of pixel_clock_dcm is 3.7 // synthesis attribute CLK_FEEDBACK of pixel_clock_dcm is NONEIn this case, clock_27mhz is the lab kit’s 27 MHz system clock and pixel_clock is thegenerated 31.5 MHz signal. The Xilinx compiler recognizes this primitive and configures one ofthe FPGA’s DCM modules accordingly. It is worth noting that the comment lines that begin withsynthesis attribute are actually pseudo-comments. That is, these lines have an effect onthe synthesis of this module; they are functional Verilog code and must be included if the DCM isto function according to our specification. By multiplying the CLKIN signal by 7 and dividing by6, we can generate a 31.5 MHz signal from our 27 MHz system clock. 2Both the horizontal and vertical sync signals are high during active video period (this is theperiod of time where pixels are displayed onto the screen). After the 640 pixels in one row, wewait 16 more clock cycles before pulling the horizontal sync signal low. This signal stays low for96 clock cycles, after which it should be set high again. We wait another 48 clock cycles beforestarting to draw the next line. The delays before and after the sync pulse are called the(horizontal) front porch and back porch, respectively. Together with the sync pulse itself, theyform the horizontal blanking period.After the horizontal blanking period of the last line of pixels, the vertical blanking period begins.This sequence is similar to the horizontal blanking period except that this only happens once perscreen refresh (i.e. every 480 lines) and the signal lengths are expressed in lines rather thanpixels. The vertical blanking period has a front porch that consists of 11 lines (yes,11*(640+16+96+48) pixels), a sync pulse that consists of 2 lines, and a back porch that is 32 linesin length. Using your 31.5 MHz clock, this leads to an approximate refresh rate of 75 Hz.a) Using the timing specifications given above for 640x480 VGA video at 75Hz, write a verilogmodule that produces horizontal and vertical sync signals. As in Lab 2, you may find it useful tocreate an FSM with one or more counters. If you take this approach, make sure your states changeafter exactly the right number of clock cycles; off-by-one errors will cause trouble. To facilitatethis, you may wish to have your counters count upwards.Your generator should input a reset signal and a 31.5 MHz pixel clock, and should output thetwo sync signals, a pixel count, and a line count. The pixel and line counts can be used to keeptrack of which pixel of the screen is currently being displayed. The pixel count represents whichpixel on the current line is being displayed. Similarly, the line count represents the current linethat is
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