6.111 Fall 2007 Lecture 4, Slide 1Introduction to VerilogIntroduction to Verilog(Combinational Logic)(Combinational Logic)Acknowledgements : Anantha Chandrakasan, Rex MinVerilog References:• Samir Palnitkar, Verilog HDL, Pearson Education (2nd edition).• Donald Thomas, Philip Moorby, The Verilog Hardware Description Language, FifthEdition, Kluwer Academic Publishers.• J. Bhasker, Verilog HDL Synthesis (A Practical Primer), Star Galaxy Publishing6.111 Fall 2007 Lecture 4, Slide 2VerilogSynthesis and Synthesis and HDLsHDLsinput a,b;output [1:0] sum;assign sum = {1b’0, a} + {1b’0, b};FPGA PALASIC(Custom ICs) Hardware description language (HDL) is a convenient, device-independent representation of digital logicNetlistg1 "and" n1 n2 n5g2 "and" n3 n4 n6g3 "or" n5 n6 n7 HDL description is compiledinto a netlist Synthesis optimizes the logic Mapping targets a specifichardware platformCompilation andSynthesisMapping6.111 Fall 2007 Lecture 4, Slide 3Synthesis and Mapping for Synthesis and Mapping for FPGAsFPGAs Infer macros: choose the FPGA macros that efficientlyimplement various parts of the HDL code Place-and-route: with area and/or speed in mind, choosethe needed macros by location and route the interconnectcounter...always @ (posedge clk)begin count <= count + 1;end...“This section of code looks likea counter. My FPGA has someof those...”HDL Code Inferred MacroMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM“This design only uses 10% of theFPGA. Let’s use the macros inone corner to minimize thedistance between blocks.”6.111 Fall 2007 Lecture 4, Slide 4Verilog: The ModuleVerilog: The Module Verilog designs consist ofinterconnected modules. A module can be an element orcollection of lower level design blocks. A simple module with combinationallogic might look like this:Declare and name a module; list itsports. Don’t forget that semicolon.Specify each port as input, output,or inoutExpress the module’s behavior.Each statement executes in parallel;order does not matter.module mux_2_to_1(a, b, out, outbar, sel);// This is 2:1 multiplexor input a, b, sel; output out, outbar; assign out = sel ? a : b; assign outbar = ~out;endmoduleConclude the module code.2-to-1 multiplexer with inverted output10seloutoutbarabComment starts with //Verilog skips from // to end of the lineOut = sel ● a + sel ● b6.111 Fall 2007 Lecture 4, Slide 5Continuous (Dataflow) AssignmentContinuous (Dataflow) Assignment Continuous assignments use the assign keyword A simple and natural way to represent combinational logic Conceptually, the right-hand expression is continuously evaluated as a function of arbitrarily-changing inputs…just like dataflow The target of a continuous assignment is a net driven by combinational logic Left side of the assignment must be a scalar or vector net or a concatenation of scalar andvector nets. It can’t be a scalar or vector register (discussed later). Right side can be registeror nets Dataflow operators are fairly low-level: Conditional operator: (conditional_expression) ? (value-if-true) : (value-if-false); Boolean logic: ~, &, |, ^ Arithmetic: +, -, * Nested conditional operator (4:1 mux) assign out = s1 ? (s0 ? i3 : i2) : (s0? i1 : i0);module mux_2_to_1(a, b, out, outbar, sel); input a, b, sel; output out, outbar; assign out = sel ? a : b; assign outbar = ~out;endmodule10seloutoutbarab6.111 Fall 2007 Lecture 4, Slide 6Gate Level DescriptionGate Level Descriptionmodule muxgate (a, b, out, outbar, sel); input a, b, sel; output out, outbar; wire out1, out2, selb; and a1 (out1, a, sel); not i1 (selb, sel); and a2 (out2, b , selb); or o1 (out, out1, out2); assign outbar = ~out;endmoduleoutoutbarselab Verilog supports basic logic gates as primitives and, nand, or, nor, xor, xnor, not, buf can be extended to multiple inputs: e.g., nand nand3in (out, in1, in2,in3); bufif1 and bufif0 are tri-state buffers Net represents connections between hardware elements. Nets aredeclared with the keyword wire.out1out2selb6.111 Fall 2007 Lecture 4, Slide 7Procedural Assignment with Procedural Assignment with alwaysalwaysmodule mux_2_to_1(a, b, out, outbar, sel); input a, b, sel; output out, outbar; reg out, outbar; always @ (a or b or sel) begin if (sel) out = a; else out = b; outbar = ~out; endendmodule Procedural assignment allows an alternative, often higher-level, behavioraldescription of combinational logic Two structured procedural statements: initial and always Supports richer, C-like control structures such as if, for, while,caseExactly the same as before.Anything assigned in an alwaysblock must also be declared as typereg (next slide)Conceptually, the always blockruns once whenever a signal in thesensitivity list changes valueStatements within the always blockare executed sequentially. Ordermatters!Surround multiple statements in asingle always block with begin/end.6.111 Fall 2007 Lecture 4, Slide 8Verilog RegistersVerilog Registers In digital design, registers represent memory elements (wewill study these in the next few lectures) Digital registers need a clock to operate and update theirstate on certain phase or edge Registers in Verilog should not be confused with hardwareregisters In Verilog, the term register (reg) simply means a variablethat can hold a value Verilog registers don’t need a clock and don’t need to bedriven like a net. Values of registers can be changedanytime in a simulation by assigning a new value to theregister6.111 Fall 2007 Lecture 4, Slide 9Mix-and-Match AssignmentsMix-and-Match Assignments Procedural and continuous assignments can (and often do) co-existwithin a module Procedural assignments update the value of reg. The value will remainunchanged till another procedural assignment updates the variable.This is the main difference with continuous assignments in which theright hand expression is constantly placed on the left-sidemodule mux_2_to_1(a, b, out, outbar, sel); input a, b, sel; output out, outbar; reg out; always @ (a or b or sel) begin if (sel) out = a; else out = b; end assign outbar = ~out;endmoduleprocedural descriptioncontinuous description10seloutaboutbar6.111 Fall 2007 Lecture 4, Slide 10The The casecase Statement Statement case and if may be used interchangeably to implementconditional execution within always blocks case is easier to read than a long
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