1.0 Introduction1.1 Document Purpose1.2 Nomenclature1.3 Conventions2.0 Device Description2.1 Product Overview2.2 Ballout DiagramsFigure 1. 3 Volt Intel StrataFlash® Memory Easy BGA BalloutFigure 2. 3 Volt Intel StrataFlash® Memory 56-Lead TSOP (32/64/128 Mbit) Offers an Easy Migration...Figure 3. 3 Volt Intel StrataFlash® Memory VF BGA Ballout(32 Mbit)2.3 Signal DescriptionsTable 1. Signal Descriptions (Sheet 1 of 2)2.4 Block DiagramFigure 4. 3 Volt Intel StrataFlash® Memory Block Diagram2.5 Memory MapFigure 5. 3 Volt StrataFlash® Memory Map3.0 Device Operations3.1 Bus OperationsTable 2. Bus OperationsTable 3. Chip Enable Truth Table3.1.1 Read Mode3.1.2 Write3.1.3 Output Disable3.1.4 Standby3.1.5 Reset/Power-Down3.2 Device CommandsTable 4. Intel StrataFlash® Memory Command Set Definitions (Sheet 1 of 2)4.0 Read Operations4.1 Read Array4.1.1 Asynchronous Page-Mode Read4.2 Read Identifier CodesTable 5. Identifier Codes4.3 Read Status RegisterTable 6. Status Register DefinitionsTable 7. eXtended Status Register Definitions4.4 Read Query/CFI5.0 Programming Operations5.1 Byte/Word Program5.2 Write to Buffer5.3 Program Suspend5.4 Program Resume6.0 Erase Operations6.1 Block Erase6.2 Block Erase Suspend6.3 Erase Resume7.0 Security Modes7.1 Set Block Lock-Bit7.2 Clear Block Lock-Bits7.3 Protection Register Program7.3.1 Reading the Protection Register7.3.2 Programming the Protection Register7.3.3 Locking the Protection RegisterFigure 6. Protection Register Memory MapTable 8. Word-Wide Protection Register AddressingTable 9. Byte-Wide Protection Register Addressing7.4 Array Protection8.0 Special Modes8.1 Set Read Configuration8.1.1 Read ConfigurationTable 10. Read Configuration Register Definition8.2 STSTable 11. STS Configuration Coding Definitions9.0 Power and Reset9.1 Power-Up/Down Characteristics9.2 Power Supply Decoupling9.3 Reset Characteristics10.0 Electrical Specifications10.1 Absolute Maximum RatingsTable 12. Absolute Maximum Ratings10.2 Operating ConditionsTable 13. Temperature and VCC Operating Conditions10.3 DC Current CharacteristicsTable 14. DC Current Characteristics10.4 DC Voltage CharacteristicsTable 15. DC Voltage Characteristics11.0 AC Characteristics11.1 Read OperationsTable 16. Read Operations (Sheet 1 of 2)Figure 7. AC Waveform for Both Page-Mode and Standard Word/Byte Read Operations11.2 Write OperationsTable 17. Write Operations11.3 Block Erase, Program, and Lock-Bit Configuration PerformanceTable 18. Configuration PerformanceFigure 8. AC Waveform for Write Operations11.4 Reset OperationFigure 9. AC Waveform for Reset OperationTable 19. Reset Specifications11.5 AC Test ConditionsFigure 10. Transient Input/Output Reference Waveform for VCCQ = 2.7 V–3.6 VFigure 11. Transient Equivalent Testing Load Circuit11.6 CapacitanceAppendix A Write State Machine (WSM)Appendix B Common Flash InterfaceTable 20. Summary of Query Structure Output as a Function of Device and ModeTable 21. Example of Query Structure Output of a x16- and x8-Capable DeviceTable 22. Query StructureTable 23. Block Status RegisterTable 24. CFI Identification (Sheet 1 of 2)Table 25. System Interface InformationTable 26. Device Geometry Definition (Sheet 1 of 2)Table 27. Primary Vendor-Specific Extended Query (Sheet 1 of 2)Table 28. Protection Register InformationTable 29. Burst Read InformationAppendix C Flow ChartsFigure 12. Write to Buffer FlowchartFigure 13. Status Register FlowchartFigure 14. Byte/Word Program FlowchartFigure 15. Program Suspend/Resume FlowchartFigure 16. Block Erase FlowchartFigure 17. Block Erase Suspend/Resume FlowchartFigure 18. Set Block Lock-Bit FlowchartFigure 19. Clear Lock-Bit FlowchartFigure 20. Protection Register Programming FlowchartAppendix D Mechanical InformationFigure 21. 3 Volt Intel StrataFlash® Memory Easy BGA Mechanical SpecificationsFigure 22. 3 Volt Intel StrataFlash® Memory VF BGA Mechanical SpecificationsAppendix E Design ConsiderationsAppendix F Additional InformationAppendix G Ordering Information3 Volt Intel StrataFlash®Memory28F128J3A, 28F640J3A, 28F320J3A (x8/x16)DatasheetProduct FeaturesCapitalizing on Intel’s 0.25 µm two-bit-per-cell technology, second generation Intel StrataFlash®memoryproducts provide 2X the bits in 1X the space, with new features for mainstream performance. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, these devices bring reliable, two-bit-per-cell storagetechnology to the flash market segment.Benefits include: more density in less space, high-speed interface, lowest cost-per-bit NOR devices, support forcode and data storage, and easy migration to future devices.Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash memorydevices take advantage of over one billion units of Flash manufacturing experience since 1987. As a result, IntelStrataFlash components are ideal for code and data applications where high density and low cost are required.Examples include networking, telecommunications, digital set top boxes, audio recording, and digital imaging.By applying FlashFile™ memory family pinouts, Intel StrataFlash memory components allow easy designmigrations from existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation IntelStrataFlash memory (28F640J5 and 28F320J5) devices.Intel StrataFlash memory components deliver a new generation of forward-compatible software support. Byusing the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantageof density upgrades and optimized write capabilities of future Intel StrataFlash memory devices. Manufacturedon Intel®0.25 micron ETOX™ VI process technology, Intel StrataFlash memory provides the highest levels ofquality and reliability.■ Performance—110/120/150 ns Initial Access Speed for32/64/128 Mbit Densities—25 ns Asynchronous Page-Mode Reads—32-Byte Write Buffer—6.8 µs per Byte EffectiveProgramming Time■ Software—Program and Erase suspend support—Flash Data Integrator (FDI), CommonFlash Interface (CFI) Compatible■ Security—128-bit Protection Register—64-bit Unique Device Identifier—64-bit User Programmable OTP Cells—Absolute Protection with VPEN=GND—Individual Block Locking—Block Erase/Program Lockout duringPower Transitions■ Architecture—Multi-Level Cell Technology: HighDensity at Low Cost—High-Density Symmetrical 128-KbyteBlocks—128 Mbit (128 Blocks)—64 Mbit (64 Blocks)—32 Mbit (32 Blocks)■ Quality and
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