Dance Dance RevoutionJacob KitzmanChris WurtsYong-yi ZhuDesign Overview• User Interface• Beta CPU•Software•Audio• VideoOverall Block DiagramUser InterfaceBeta CPU• Non-pipelined, 4.5 MIPS @ 27 MHzi386 (1993): 5 MIPS @ 16 MHz• Full support for beta ISA– RISC “Load-Store” Architecture• Shared memory bus– Bus controller arbitrates access to main memory between up to 8 devices.Beta Block Diagram(this should look familiar…)Bus Access MechanismDDR Software• Determine current time.• Look at list of “correct” steps. – Any past by > ¾ sec? No points! Advance ptr.– Any recently (<¾ sec) past? If matches user input, award points = f(user_time-correct_time). Dequeueinput & advance correct step ptr.• Any more user input?– Steps are early! If < ¾ sec early, award points on same function as before. Dequeue input & advace correct step ptr.• Rebuild display with upcoming steps & score– Gradient background + bilblt’d gliphs (text, arrows, etc.)AudioVideoVideoQ &
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