1. Read and understand the whole assignment.2. Design, build, test, debug, and fix each exercise in turn. Be sure to answer all the questions in the report template before you get checked off. You do NOT have to get checked-off on a exercise before proceeding to the next one. For each ...3. Do not use the power supply from the labkit to power the external proto board. Use the bench power supply. Problems 1-7 should not use the FPGA labkit and should be done on the external breadboard.Figure 1 : (a) Logic Level Measurement (Measure voltage at OUT node). (b) Power Supply Wiring.Figure 2 : Timing Characteristics (10%, 50%, 90% marked).Figure 3 : Ring Oscillator (using a 74LS04).Figure 4 : Glitch Measurement Circuit (74LS00).Figure 5 : Clock and Ripple Counter.Figure 6 : Synchronous Counter Wiring (RCO of the first chip is only connected to T, not +5).Figure 7 : Setup for SR Latch.Figure 8 : (a) The ten segmented digits. (b) shows the mapping of outputs a-g to segments.Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory (Spring 2006) Laboratory 1 - Introduction to Digital Electronics and Lab Equipment (Logic Analyzers, Digital Oscilloscope, and FPGA-based Labkit) Issued: February 8, 2006 Checkoff and Report Due in Class (1PM) on: February 22, 2006 Introduction This lab assignment introduces you to important tools and devices that we will be using through-out the term. You will be introduced to the following: • Logic analyzer and digital scope. • 74LS TTL series chips, including the ‘00, ‘04, ‘163, ‘393, ‘74 • 74HC00, a CMOS NAND gate • 1.8432 MHz Crystal Oscillator • TTL and CMOS voltage levels • Karnaugh Maps and Boolean Algebra • Latches and Flip-flops, Simple Sequential and Asynchronous circuits • Simple Verilog • ModelSim (Verilog simulator), Xilinx FPGA labkit, Xilinx programming software The following are relevant handouts that you should be using in conjunction with this lab: • Lectures 1-5 •Safety Memo Procedure This lab is divided into several exercises to guide you through the design, construction, and debugging process. You will be asked to wire circuits for many of the exercises. Save all of these circuits until you have completed the lab as many of these circuits might be reused in subsequent parts of this lab. 1. Read and understand the whole assignment. 2. Design, build, test, debug, and fix each exercise in turn. Be sure to answer all the questions in the report template before you get checked off. You do NOT have to get checked-off on a exercise before proceeding to the next one. For each exercise, be sure to have the appropriate figures ready. Turn in the completed report template after your checkoff. 3. Do not use the power supply from the labkit to power the external proto board. Use the bench power supply. Problems 1-7 should not use the FPGA labkit and should be done on the external breadboard. 1Exercise 1: TTL/CMOS Static DC Characteristics The logic values of 1 and 0 are represented by voltage levels in the hardware implementation. The voltage levels and other electrical characteristics are not standardized from one logic family to another. 6.111 will use both TTL (Transistor-Transistor Logic) and CMOS (Complementary Metal-Oxide Semiconductor) logic. The voltage ranges for the two logic families are different. In this exercise, you will first measure the electrical characteristics of a TTL and CMOS gate using the circuit in Figure 1. Wire up this circuit using a 74LS00 part. Do not forget to wire power and ground! These connections are usually omitted from logic diagrams, as the power and ground of the 74LS series are generally the top-right and bottom-left pin, respectively. Typically, the top of the chip has a small semi-circular cutout, or a white dot next to pin 1. Ground the input of the inverter (the first NAND) and measure the output voltage using the oscil-loscope. Be sure to be using the voltage markers on the oscilloscope. Connect the input to a logic ‘1’ and repeat the measurement. +5 +5 1 3 OUTIN 2 Ground 1 7 8 14 74LS00 Figure 1: (a) Logic Level Measurement (Measure voltage at OUT node). (b) Power Supply Wiring. Next, use a 74HC00 and wire up the same circuit and hook VCC to a +5V supply. Perform the same measurements and record your results. Look up the valid input and output voltage ranges using the datasheet for a 74LS00 and a 74HC00. For each experiment, do your output values satisfy the range specified in the datasheets? Consider interfacing a TTL inverter to a CMOS inverter and vice versa. Look at the datasheet titled “HCMOS Family Characteristics”. Based on the +5V supply you used, find out the recom-mended input voltage for HCMOS inputs. Discuss potential issues when interfacing TTL and CMOS components? Run the two experiments (interface TTL to CMOS and vice versa) and make voltage measurements. 2Exercise 2: Build Your Own Ring Oscillator Important timing parameters associated with the speed of digital logic gates are the propagation delay time tPD, and the output signal rise and fall times, tr and tf. Propagation delay is a measure of how much time is required for a signal to change state. It is measured as the time from the 50% point of the input to the 50% point of the output (Figure 2). It is often cited as the average of the high-to-low and low-to-high delays (corresponding to the two transitions). The rise and fall times represent the amount of time for a signal to change state. To measure rise and fall times, you should be using the 10% to the 90% point, or vice versa. In tfallOut tPD trise Figure 2: Timing Characteristics (10%, 50%, 90% marked). Construct the ring oscillator shown in Figure 3 using a 74LS04 with as little wire as possible. From this circuit, determine the average propagation delay of a TTL inverter by measuring the period of oscillation by using the time markers on the oscilloscope. You can determine this by determining the number of gates a signal must travel through to complete a full period of oscilla-tion. What should the period of oscillation be with 3 inverters in the ring? Rewire the circuit and mea-sure the period. Comment on the new result. Insert a long piece of wire (about 3 feet) into the ring of 3 inverters. Observe how this extra length of circuit affects the signal. Can you explain the change? 1 2 3 4 5 6 13 12 1011 Figure 3: Ring Oscillator
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