L4: Sequential Building Blocks (Flip-flops, Latches and Registers)Combinational Logic ReviewA Sequential SystemA Simple ExampleImplementing State: Bi-stabilityNOR-based Set-Reset (SR) FlipflopMaking a Clocked Memory Element: Positive D-LatchMultiplexer Based Positive & Negative Latch74HC75 (Positive Latch)Building an Edge-Triggered RegisterLatches vs. Edge-Triggered Register Important Timing Parameters74HC74 (Positive Edge-Triggered Register)The J-K Flip-FlopJ-K Master-Slave RegisterPulse Based Edge-Triggered J-K RegisterPulse-Triggered RegistersD Flip-Flop vs. Toggle Flip-Flop Realizing Different Types of Memory ElementsDesign ProcedureDesign Procedure (cont.)System Timing ParametersSystem Timing (I): Minimum PeriodSystem Timing (II): Minimum DelayShift-RegisterL4: 6.111 Spring 2008 1Introductory Digital Systems LaboratoryL4: Sequential Building BlocksL4: Sequential Building Blocks (Flip(Flip--flops, Latches and Registers)flops, Latches and Registers)Acknowledgements: ¾Lecture material adapted from R. Katz, G. Borriello, “Contemporary Logic Design”(second edition), Prentice-Hall/Pearson Education, 2005. ¾Lecture material adapted from J. Rabaey, A. Chandrakasan, B. Nikolic, “Digital Integrated Circuits: A Design Perspective” Copyright 2003 Prentice Hall/Pearson.¾Lecture notes prepared by Professor Anantha ChandrakasanL4: 6.111 Spring 2008 2Introductory Digital Systems LaboratoryCombinational Logic ReviewCombinational Logic Review Combinational logic circuits are memoryless No feedback in combinational logic circuits Output assumes the function implemented by the logic network, assuming that the switching transients have settled Outputs can have multiple logical transitions before settling to the correct valueCombinationalCircuit in0in1inN-1in0in1inM-1L4: 6.111 Spring 2008 3Introductory Digital Systems LaboratoryA Sequential SystemA Sequential System Sequential circuits have memory (i.e., remember the past) The current state is “held” in memory and the next state is computed based the current state and the current inputs In a synchronous systems, the clock signal orchestrates the sequence of eventsCOMBINATIONALLOGICRegistersOutputsNext stateCLKQDCurrent StateInputsMemory elementL4: 6.111 Spring 2008 4Introductory Digital Systems LaboratoryA Simple ExampleA Simple Examplein0in1in2inN-1Adding N inputs (N-1 Adders)inD QresetclkCurrent_SumUsing a sequential (serial) approachL4: 6.111 Spring 2008 5Introductory Digital Systems LaboratoryImplementing State: BiImplementing State: Bi--stabilitystabilityVi1ACBVo2Vi1= Vo2Vo1Vi2Vi2= Vo1Vo1 =Vi2Vo2 =Vi1Point C is MetastableVi2=VoVi1= Vo2AδVi2=Vo1Vi1= Vo2Cδ1Points A andB are stable(represent 0 & 1)BL4: 6.111 Spring 2008 6Introductory Digital Systems LaboratoryNORNOR--based Setbased Set--Reset (SR) Reset (SR) FlipflopFlipflop Flip-flop refers to a bi-stable element (edge-triggered registers are also called flip-flops) – this circuit is not clocked and outputs change “asynchronously” with the inputsQ Q Q QQ Q0 11 00 0SR = 1 0SR = 0 1SR = 0 1SR = 1 1SR = 1 0SR = 1 1SR = 00, 01SR = 00, 10SR = 0 0SR = 11SR = 0 0Forbidden StateSSRQQQQRS QQ00 Q101 0010 1011 0RQResetHoldSet SetResetRSQQ??L4: 6.111 Spring 2008 7Introductory Digital Systems LaboratoryMaking a Clocked Memory Element:Making a Clocked Memory Element: Positive DPositive D--LatchLatchCLKDQD Qclk A Positive D-Latch: Passes input D to output Q when CLK is high and holds state when clock is low (i.e., ignores input D) A Latch is level-sensitive: invert clock for a negative latchSRclockR and Ssample holdsample holdholdGL4: 6.111 Spring 2008 8Introductory Digital Systems LaboratoryMultiplexer Based Positive & Negative LatchMultiplexer Based Positive & Negative Latch10in0in1outSELOut = sel * in1 + sel * in0 2:1 multiplexer10DQCLKPositive Latch01DQCLKNegative Latch"remember""load""data""stored value"clkclkL4: 6.111 Spring 2008 9Introductory Digital Systems Laboratory74HC75 (Positive Latch)74HC75 (Positive Latch)L4: 6.111 Spring 2008 10Introductory Digital Systems LaboratoryBuilding an EdgeBuilding an Edge--Triggered RegisterTriggered Register Master-Slave Register Use negative clock phase to latch inputs into first latch Use positive clock to change outputs with second latch View pair as one basic unit master-slave flip-flop twice as much logicDGQ DGQClkDNegative latch Positive latch10DCLKQMMaster01CLKQSlaveQMQDCLKQDClkQQDQML4: 6.111 Spring 2008 11Introductory Digital Systems LaboratoryLatches vs. EdgeLatches vs. Edge--Triggered Register Triggered Register Edge triggered device sample inputs on the event edgeTransparent latches sample inputs as long as the clock is assertedTiming Diagram:Behavior the same unless input changes while the clock is high74747475Bubble herefor negativeedge triggeredregisterPositive edge-triggered registerLevel-sensitive latch D Q D Q C ClkClkD ClkQ Q 7474 7475L4: 6.111 Spring 2008 12Introductory Digital Systems LaboratoryImportant Timing ParametersImportant Timing ParametersSetup Time (Tsu )Clock: Periodic Event, causes state of memoryelement to changememory element can be updated on the: rising edge, falling edge, high level, low levelThere is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognizedThere is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognizedMinimum time before the clocking event by which the input must be stableHold Time (Th )Minimum time after the clocking event during which the input must remain stableInput Clock T suT h Propagation Delay (Tcq for an edge-triggered register and Tdq for a latch)Delay overhead of the memory elementL4: 6.111 Spring 2008 13Introductory Digital Systems Laboratory74HC74 (Positive Edge74HC74 (Positive Edge--Triggered Register)Triggered Register)74HC74(courtesy TI)D-FF with preset and clearL4: 6.111 Spring 2008 14Introductory Digital Systems LaboratoryThe JThe J--K FlipK Flip--FlopFlopSRQQJK Eliminate the forbidden state of the SR Flip-flop Use output feedback to guarantee that R and S are never both oneJ K Q+ Q+0 0 Q Q0 1 0 11 0 1 01 1 Q QJ K Q \ Q 100L4: 6.111 Spring 2008 15Introductory Digital Systems LaboratoryJJ--K MasterK Master--Slave RegisterSlave RegisterSRQQJKSRQQCLKSample inputs while clock highSample inputs while clock lowCorrect ToggleOperationMaster outputs Slave outputs Set Reset T
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