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MIT 6 111 - Synchronization

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L6: FSMs and SynchronizationAsynchronous Inputs in Sequential SystemsAsynchronous Inputs in Sequential SystemsHandling MetastabilityFinite State MachinesReview: FSM Timing RequirementsTwo Types of FSMsDesign Example: Level-to-PulseState Transition DiagramsLogic Derivation for a Moore FSMMoore Level-to-Pulse ConverterDesign of a Mealy Level-to-PulseMealy Level-to-Pulse ConverterMoore/Mealy Trade-OffsThe 6.111 Vending MachineWhat States are in the System?A Moore VenderState ReductionVerilog for the Moore VenderVerilog for the Moore VenderSimulation of Moore VenderCoding Alternative: Two BlocksFSM Output GlitchingRegistered FSM Outputs are Glitch-FreeMealy Vender (covered in Recitation)Verilog for Mealy FSMVerilog for Mealy FSMSimulation of Mealy VenderDelay Estimation : Simple RC NetworksClocks are Not Perfect: Clock SkewPositive and Negative SkewClocks are Not Perfect: Clock JitterSummaryL6: 6.111 Spring 2007 1Introductory Digital Systems LaboratoryL6: L6: FSMsFSMsand Synchronizationand SynchronizationLecture material courtesy of Rex MinL6: 6.111 Spring 2007 2Introductory Digital Systems LaboratoryAsynchronous Inputs in Sequential SystemsAsynchronous Inputs in Sequential SystemsWhat about external signals?Can’t guarantee setup and hold times will be met!Sequential SystemClockWhen an asynchronous signal causes a setup/hold violation...I IIIClockQDII?Output is metastablefor an indeterminate amount of time.Transition is missed on first clock cycle, but caught on next clock cycle.Transition is caught on first clock cycle.Q: Which cases are problematic?L6: 6.111 Spring 2007 3Introductory Digital Systems LaboratoryAsynchronous Inputs in Sequential SystemsAsynchronous Inputs in Sequential SystemsAll of them can be, if more than one happens simultaneously within the same circuit.Idea: ensure that external signals directly feed exactly one flip-flopD QD QQ0ClockClockQ1AsyncInputClocked Synchronous SystemDQSequential SystemClockThis prevents the possibility of I and II occurring in different places in the circuit, but what about metastability?L6: 6.111 Spring 2007 4Introductory Digital Systems LaboratoryHandling Handling MetastabilityMetastability Preventing metastability turns out to be an impossible problem High gain of digital devices makes it likely that metastable conditions will resolve themselves quickly Solution to metastability: allow time for signals to stabilizeLikeley to be metastableright after samplingExtremely unlikely to be metastable for >2 clock cycleVery unlikely to be metastable for >1 clock cycleDQComplicated Sequential Logic SystemDQDQClockHow many registers are necessary? Depends on many design parameters(clock speed, device speeds, …) In 6.111, one or maybe two synchronization registers is sufficientL6: 6.111 Spring 2007 5Introductory Digital Systems LaboratoryFinite State MachinesFinite State Machines Finite State Machines (FSMs) are a useful abstraction for sequential circuits with centralized “states” of operation At each clock edge, combinational logic computes outputs and next state as a function of inputs and present stateCombinationalLogicFlip-FlopsQDinputs+presentstateoutputs+nextstatennCLKL6: 6.111 Spring 2007 6Introductory Digital Systems LaboratoryReview: FSM Timing RequirementsReview: FSM Timing Requirements Timing requirements for FSM are identical to any generic sequential system with feedbackCombinationalLogicFlip-FlopsQDCLKinputs+presentstateoutputs+nextstatennTcqTsuTlogicCombinationalLogicFlip-FlopsQDCLKinputs+presentstatenoutputs+nextstatenTcq,cdTholdTTlogic,cdMinimum Clock Period Minimum DelayTcq,cd+ Tlogic,cd> TholdT > Tcq+ Tlogic+ TsuL6: 6.111 Spring 2007 7Introductory Digital Systems LaboratoryTwo Types of Two Types of FSMsFSMsMoore and Mealy FSMs are distinguished by their output generationinputsx0...xnMoore FSM:Comb.LogicCLKnFlip-FlopsComb.LogicDQpresent state SnnextstateS+outputsyk= fk(S)Mealy FSM:SComb.LogicCLKFlip-FlopsComb.LogicDQnS+ndirect combinational path!outputsyk= fk(S, x0...xn)inputsx0...xnL6: 6.111 Spring 2007 8Introductory Digital Systems LaboratoryDesign Example: LevelDesign Example: Level--toto--PulsePulse A level-to-pulse converter produces a single-cycle pulse each time its input goes high. In other words, it’s a synchronous rising-edge detector. Sample uses: Buttons and switches pressed by humans for arbitrary periods of time Single-cycle enable signals for countersLevel toPulseConverterLPCLK...output P produces a single pulse, one clock period wide.Whenever input L goes from low to high...L6: 6.111 Spring 2007 9Introductory Digital Systems LaboratoryState Transition DiagramsState Transition Diagrams Block diagram of desired system: State transition diagram is a useful FSM representation and design aid00Low input, Waiting for riseP = 001Edge Detected!P = 1High input,Waiting for fallDQLevel toPulseFSMLPunsynchronizeduser inputSynchronizerEdge DetectorL=1This is the output that results from this state. (Moore or Mealy?)L=0P = 011Binary values of statesL=0L=0L=1“if L=0 at the clock edge, then stay in state 00.”“if L=1 at the clock edge, then jump to state 01.”DQCLKL=1L6: 6.111 Spring 2007 10Introductory Digital Systems LaboratoryLogic Derivation for a Moore FSMLogic Derivation for a Moore FSM Transition diagram is readily converted to a state transition table (just a truth table)00Low input, Waiting for riseP = 001Edge Detected!P = 111High input,Waiting for fallP = 0L=1L=1L=0L=0L=1L=0Current StateNext State OutInS1L01010S1+S0+10P0011010100100010100S0000 1011111 Combinational logic may be derived by Karnaugh mapsComb.LogicCLKnFlip-FlopsComb.LogicDQSnS+X1101X000010110100X1111X000010110100S1S0LS1S0Lfor S1+:for S0+:011X0010S1for P:LPS0S1+= LS0S0+= LS1+= LS0S0+= LP = S1S0P = S1S0L6: 6.111 Spring 2007 11Introductory Digital Systems LaboratoryMoore LevelMoore Level--toto--Pulse ConverterPulse Converterinputsx0...xnComb.LogicCLKnFlip-FlopsComb.LogicDQpresent state SnnextstateS+outputsyk= fk(S)S1+= LS0S0+= LS1+= LS0S0+= LP = S1S0P = S1S0Moore FSM circuit implementation of level-to-pulse converter:DQDQS0S1CLKS0+S1+LPQQL6: 6.111 Spring 2007 12Introductory Digital Systems LaboratoryDesign of a Mealy LevelDesign of a Mealy Level--toto--PulsePulseSComb.LogicCLKFlip-FlopsComb.LogicDQnS+ndirect combinational path! Since outputs are determined by state and inputs, Mealy FSMs may need fewer states than Moore FSM implementations0Input is low1Input is highPLStateClock1.


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MIT 6 111 - Synchronization

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