PRELIMINARY512Kx36/1Mx18 Pipelined SRAM with NoBL™ ArchitectureCY7C1370CCY7C1372C Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600Document #: 38-05233 Rev. *A Revised November 19, 2002Features• Zero Bus Latency™, no dead cycles between write and read cycles• Fast clock speed: 250, 225, 200, and 167 MHz• Fast access time: 2.6, 2.8, 3.0, 3.4 ns• Internally synchronized registered outputs eliminate the need to control OE• Single 3.3V –5% and +10% power supply VDD• Separate VDDQ for 3.3V or 2.5V I/O•Single WE (Read/Write) control pin• Positive clock-edge triggered address, data, and con-trol signal registers for fully pipelined applications• Interleaved or linear 4-word burst capability• Individual byte write (BWSa–BWSd) control (may be tied LOW)•CEN pin to enable clock and suspend operations• Three chip enables for simple depth expansion • JTAG boundary scan (BGA and FBGA Packages Only)• Available in 119-ball bump BGA, 165-ball FBGA and 100-pin TQFP packages• Automatic power down available using ZZ mode or CE deselectFunctional DescriptionThe CY7C1370C and CY7C1372C SRAMs are designed toeliminate dead cycles when transitions from Read to Write orvice versa. These SRAMs are optimized for 100 percent busutilization and achieve Zero Bus Latency. They integrate524,288x36 and 1,048,576x18 SRAM cells, respectively, withadvanced synchronous peripheral circuitry and a 2-bit counterfor internal burst operation. The Synchronous Burst SRAMfamily employs high-speed, low-power CMOS designs usingadvanced single-layer polysilicon, three-layer metal technolo-gy. Each memory cell consists of six transistors.All synchronous inputs are gated by registers controlled by apositive-edge-triggered Clock Input (CLK). The synchronousinputs include all addresses, all data inputs, depth-expansionchip enables (CE1, CE2, and CE3), cycle start input (ADV/LD),Clock Enable (CEN), byte write enables (BWSa, BWSb,BWSc, and BWSd), and read-write control (WE). BWSc andBWSd apply to CY7C1370C only.Address and control signals are applied to the SRAM duringone clock cycle, and two cycles later, its associated data oc-curs, either read or write.A clock enable (CEN) pin allows operation of theCY7C1370C/CY7C1372C to be suspended as long as neces-sary. All synchronous inputs are ignored when CEN is HIGHand the internal device registers will hold their previous values.There are three chip enable pins (CE1, CE2, CE3) that allowthe user to deselect the device when desired. If any one ofthese three are not active when ADV/LD is LOW, no new mem-ory operation can be initiated and any burst cycle in progressis stopped. However, any pending data transfers (read orwrite) will be completed. The data bus will be in high-imped-ance state two cycles after the chip is deselected or a writecycle is initiated.The CY7C1370C and CY7C1372C have an on-chip 2-bit burstcounter. In the burst mode, the CY7C1370C and CY7C1372Cprovide four cycles of data for a single address presented tothe SRAM. The order of the burst sequence is defined by theMODE input pin. The MODE pin selects between linear andinterleaved burst sequence. The ADV/LD signal is used to loada new external address (ADV/LD = LOW) or increment theinternal burst counter (ADV/LD = HIGH)Output enable (OE) and burst sequence select (MODE) arethe asynchronous signals. OE can be used to disable the out-puts at any given time. ZZ may be tied to LOW if it is not used.Four pins are used to implement JTAG test capabilities. TheJTAG circuitry is used to serially shift data to and from thedevice. JTAG inputs use LVTTL/LVCMOS levels to shift dataduring this testing mode of operation. CLKAxCENWEBWSxCE1CECE2OE512K x 36/MEMORYARRAYLogic Block DiagramDQxData-In REG.QDCECONTROLand WRITELOGIC3ADV/LDModeDPxCY7C1370C CY7C1372C AXDQXDPXBWSX1M x 18X = 18:0 X = 19:0X = a, b, c, d X = a, bX = a, bX = a, bX = a, b, c, dX = a, b, c, d OUTOUTREGISTERS and LOGICCY7C1370CCY7C1372CPRELIMINARY Document #: 38-05233 Rev. *A Page 2 of 29.Selection Guide250 MHz 225 MHz 200 MHz 167 MHz UnitMaximum Access Time 2.6 2.8 3.0 3.4 nsMaximum Operating Current 350 325 300 275 mAMaximum CMOS Standby Current 70 70 70 70 mAShaded areas contain advance information.Pin ConfigurationsAAAAA1A0VSSVDDAAAAAAVDDQVSSDQb DQb DQb VSSVDDQDQb DQb VSSNC VDDDQaDQaVDDQVSSDQaDQaVSSVDDQVDDQVSSDQc DQc VSSVDDQDQc DQc VDDVSSDQd DQd VDDQVSSDQdDQdDQdVSSVDDQAACE1CE2BWSaCE3VDDVSSCLKWECENOEAA123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495080797877767574737271706968676665646362616059585756555453525110099989796959493929190898887868584838281AAADV/LDZZ CY7C1370C 100-Pin TQFP PackagesAAAAA1A0NCVSSVDDAAAAAAANCNCVDDQVSSNCDPaDQa DQaVSSVDDQDQaDQaVSSNC VDDDQaDQaVDDQVSSDQaDQaNCNCVSSVDDQNCNCNCNCNCNCVDDQVSSNCNCDQbDQbVSSVDDQDQbDQbNCVDDVSSDQbDQbVDDQVSSDQbDQbDPbNCVSSVDDQNCNCNCAACE1CE2NCNCBWSbBWSaCE3VDDVSSCLKWECENOEAAA123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495080797877767574737271706968676665646362616059585756555453525110099989796959493929190898887868584838281AAADV/LDZZ MODE CY7C1372C BWSdMODE BWScDQcDQcDQcDQcDPcDQdDQdDPdDQdNCDPbDQbDQaDQaDQaDQaDPaDQbDQb(512K x 36)(1M x 18)BWSbNCNCANCNCNCNCNCNCNCCY7C1370CCY7C1372CPRELIMINARY Document #: 38-05233 Rev. *A Page 3 of 29Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUDQaVDDQNCNCDQcDQdDQcDQdAA AAAVDDQCE2AVDDQVDDQVDDQVDDQNCNCADQcDQcDQdDQd TMSVDDA72MDPdAAADV/LDACE3NCVDDAANCVSSVSSNC DPbDQbDQbDQaDQbDQbDQaDQaNCTDI TDO VDDQTCKVSSVSSVSSNCVSSVSSVSSVSSMODECE1VSSOE VSSVDDQBWScAVSSWEVDDQVDDNC VDDVSSCLKNC BWSaCENVSSVDDQVSSZZNCAAA1A0 VSSVDDNCCY7C1370C (512K x 36) - 7 x 17 BGADPc DQbA36MDQc DQbDQcDQcDQcDQbDQbDQaDQaDQaDQaDPaDQdDQdDQdDQdBWSd119-Ball Bump BGABWSb2345671ABCDEFGHJKLMNPRTU36MDQaVDDQNCNCNCDQbDQbDQbDQbAA AAAVDDQCE2ANCVDDQNCVDDQVDDQVDDQNCNCNC72MADQbDQbDQbDQbNCNCNCNCTMSVDDAADPbAAADV/LDACE3NCVDDAANCVSSVSSNC NCDPaDQaDQaDQaDQaDQaDQaDQaNCTDI TDO VDDQTCKVSSVSSVSSNCVSSVSSVSSVSSVSSMODECE1VSSNCOEVSSVDDQBWSbA VSSNCVSSWE NCVDDQVDDNC VDDNCVSSCLKNC NCBWSaCENVSSNC VDDQVSSNCZZNCAAAA1A0 VSSNCVDDNCCY7C1372C (1M x 18) - 7 x 17 BGACY7C1370CCY7C1372CPRELIMINARY Document #: 38-05233 Rev. *A Page 4 of 29Pin Configurations (continued)CY7C1370C (512K x 36) - 11 x 15 FBGA165-Ball Bump FBGACY7C1372C (1M x 18) - 11 x 15 FBGA2345671ABCDEFGHJKLMNPRTDONCNCNCNCDPbNCDQbACE1NC CE3BWSbCENACE2NCDQbDQbMODENCDQbDQbNCNC NC36M72MVDDQNC BWSa CLK
View Full Document
Unlocking...