L3: Introduction to Verilog (Combinational Logic)Synthesis and HDLsVerilog: The ModuleContinuous (Dataflow) AssignmentGate Level DescriptionProcedural Assignment with alwaysVerilog RegistersMix-and-Match AssignmentsThe case StatementThe Power of Verilog: n-bit SignalsConcatenate signals using the { } operatorThe Power of Verilog: Integer ArithmeticDangers of Verilog: Incomplete SpecificationIncomplete Specification Infers LatchesAvoiding Incomplete SpecificationDangers of Verilog: Priority LogicPriority LogicAvoiding (Unintended) Priority LogicInterconnecting ModulesModule DefinitionsTop-Level ALU DeclarationModelSim OutputMore on Module InterconnectionUseful Boolean OperatorsModelSim/Testbench Introduction: Demo this week in Lab by TAsSummaryL3: 6.111 Spring 2007 1Introductory Digital Systems LaboratoryL3: Introduction to L3: Introduction to VerilogVerilog (Combinational Logic)(Combinational Logic)Acknowledgements : Rex MinLecture Notes prepared by Professor Anantha ChandrakasanVerilog References:• Samir Palnitkar, Verilog HDL, Pearson Education (2nd edition).• Donald Thomas, Philip Moorby, The Verilog Hardware Description Language, Fifth Edition, Kluwer Academic Publishers. • J. Bhasker, Verilog HDL Synthesis (A Practical Primer), Star Galaxy PublishingL3: 6.111 Spring 2007 2Introductory Digital Systems LaboratoryVerilogSynthesis and Synthesis and HDLsHDLsinput a,b;output sum;assign sum = {1b’0, a} + {1b’0, b};FPGA PALASIC (Custom ICs) Hardware description language (HDL) is a convenient, device-independent representation of digital logicNetlistg1 "and" n1 n2 n5 g2 "and" n3 n4 n6 g3 "or" n5 n6 n7 HDL description is compiled into a netlist Synthesis optimizes the logic Mapping targets a specific hardware platformCompilation and SynthesisMappingL3: 6.111 Spring 2007 3Introductory Digital Systems LaboratoryVerilogVerilog: The Module: The Module Verilog designs consist of interconnected modules. A module can be an element or collection of lower level design blocks. A simple module with combinational logic might look like this:Declare and name a module; list its ports. Don’t forget that semicolon.Specify each port as input, output, or inoutExpress the module’s behavior. Each statement executes in parallel; order does not matter.module mux_2_to_1(a, b, out, outbar, sel);// This is 2:1 multiplexorinput a, b, sel;output out, outbar;assign out = sel ? a : b;assign outbar = ~out; endmoduleConclude the module code.2-to-1 multiplexer with inverted output10seloutoutbarabComment starts with // Verilog skips from // to end of the lineOut = sel ● a + sel ● bL3: 6.111 Spring 2007 4Introductory Digital Systems LaboratoryContinuous (Dataflow) AssignmentContinuous (Dataflow) Assignment Continuous assignments use the assign keyword A simple and natural way to represent combinational logic Conceptually, the right-hand expression is continuously evaluated as a function of arbitrarily-changing inputs…just like dataflow The target of a continuous assignment is a net driven by combinational logic Left side of the assignment must be a scalar or vector net or a concatenation of scalar and vector nets. It can’t be a scalar or vector register (discussed later). Right side can be register or nets Dataflow operators are fairly low-level: Conditional assignment: (conditional_expression) ? (value-if-true) : (value-if-false); Boolean logic: ~, &, | Arithmetic: +, -, * Nested conditional operator (4:1 mux) assign out = s1 ? (s0 ? i3 : i2) : (s0? i1 : i0);module mux_2_to_1(a, b, out, outbar, sel);input a, b, sel;output out, outbar;assign out = sel ? a : b;assign outbar = ~out; endmodule10seloutoutbarabL3: 6.111 Spring 2007 5Introductory Digital Systems LaboratoryGate Level DescriptionGate Level Descriptionmodule muxgate (a, b, out, outbar, sel);input a, b, sel;output out, outbar;wire out1, out2, selb;and a1 (out1, a, sel);not i1 (selb, sel);and a2 (out2, b , selb);or o1 (out, out1, out2);assign outbar = ~out; endmoduleoutoutbarselab Verilog supports basic logic gates as primitives and, nand, or, nor, xor, xnor, not, buf can be extended to multiple inputs: e.g., nand nand3in (out, in1, in2,in3); bufif1 and bufif0 are tri-state buffers Net represents connections between hardware elements. Nets are declared with the keyword wire. out1out2selbL3: 6.111 Spring 2007 6Introductory Digital Systems LaboratoryProcedural Assignment with Procedural Assignment with alwaysalwaysmodule mux_2_to_1(a, b, out, outbar, sel);input a, b, sel;output out, outbar;reg out, outbar; always @ (a or b or sel)beginif (sel) out = a;else out = b;outbar = ~out;end endmodule Procedural assignment allows an alternative, often higher-level, behavioral description of combinational logic Two structured procedure statements: initial and always Supports richer, C-like control structures such as if, for, while,caseExactly the same as before.Anything assigned in an always block must also be declared as type reg (next slide)Conceptually, the always block runs once whenever a signal in the sensitivity list changes valueStatements within the always block are executed sequentially. Order matters!Surround multiple statements in a single always block with begin/end.L3: 6.111 Spring 2007 7Introductory Digital Systems LaboratoryVerilogVerilog RegistersRegisters In digital design, registers represent memory elements (we will study these in the next few lectures) Digital registers need a clock to operate and update their state on certain phase or edge Registers in Verilog should not be confused with hardware registers In Verilog, the term register (reg) simply means a variable that can hold a value Verilog registers don’t need a clock and don’t need to be driven like a net. Values of registers can be changed anytime in a simulation by assuming a new value to the registerL3: 6.111 Spring 2007 8Introductory Digital Systems LaboratoryMixMix--andand--Match AssignmentsMatch Assignments Procedural and continuous assignments can (and often do) co-exist within a module Procedural assignments update the value of reg. The value will remain unchanged till another procedural assignment updates the variable. This is the main difference with continuous assignments in which the right hand expression is constantly placed on the left-sidemodule mux_2_to_1(a, b, out, outbar, sel);input a, b, sel;output out, outbar;reg out; always
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