Wireless Security SystemVideo Surveillance Block DiagramVideo Capture OverviewTechnical ConsiderationsVideo CompressionVideo EncoderWireless TransmissionTransmitterReceiverVideo DecoderVideo Display OverviewWireless Security SystemNoel CampbellVivek ShahRaymond TongVideo Surveillance Block DiagramVideo Capture OverviewCameraADV7185Composite Intv_in_ycrcb[19:0]Clock_27MHztv_clockMemory ControllerDual-Port Block MemoryVGA Controllerycrcb [29:0]XWEYADDRYCrCb to RGB ConverterDisplayNTSC Decoder2030AsyncFIFOClock_27MHzZRGBSyncing and blanking signalsencode_busywriting_memoryY isolator8Y [7:0]Technical Considerations Synchronization of data ADV7185 clock vs lab kit 27 MHz clock Displaying data in VGA Acquire 240 X 240 real time video Write data to block memory then continuously read from itMemory Controller Write a frame worth of data into block memory for encoding and transmissionVideo CompressionDiscrete Cosine TransformInverse Discrete Cosine Transform512 bits/block56 bits/blockVideo Encoder8Dual PortBlock Memory(64x900)Dual PortBlock Memory(64x900)Dual PortBlock Memory(64x900)Dual PortBlock Memory(64x900)Dout64Dout64Dout64Dout64Multiplier BlockFinite State MachineAddress (10)Adder BlockAndTruncate ModuleMatrix_int0144Matrix_int1144Matrix_int2144Matrix_int3144144Multiplier BlockAdder Block288288288288DCT CoefficientsDCT CoefficientsEncoding_line (10)Wireless_busyDual PortBlock Memory(80x900)Address (10) and WELine_write (5)Wireless Transmission Data is sent serially from the labkit to the wireless kit Data is assembled into packets and sent from camera-end to fixed-end via CC2420 radio Data is then sent serially from receiver wireless kit to the receiver labkitTransmitterfrom encoder80 x 900Dual Port BRAM80RadioTransmitterserialcableTransmitter Control UnitShiftRegisterRS232Sender8to receiverFPGA microcontrollerReceiverfrom transmitter80 x 900Dual Port BRAMTransmitter Control UnitRS232ReceiverShiftRegister80RadioReceiverserialcableto decodermicrocontroller FPGAVideo DecoderAddressRegisters(80)Dout80Multiplier BlockFinite State MachineAdder BlockMatrix_int0144Matrix_int1144144144144144Multiplier BlockAdder Block288288288288DCT CoefficientsDCT CoefficientsLINE_DONE (5)LINE_READ (5)Address (10) and WEBlock_doneReadyDual PortBlock Memory(64x900)Dual PortBlock Memory(64x900)Dual PortBlock Memory(64x900)Dual PortBlock Memory(64x900)64646464Video Display OverviewClock_27MHzto all modulesY [7:0]Dual-Port Block Memory8VGA ControllerYCrCb to RGB ConverterDisplayRGBZDelayAddr XZSyncing and blanking signals* Only chrominance (Y) is important if displaying grayscale image Memory
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